Patents by Inventor Hinoko Kurosawa

Hinoko Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
    Patent number: 5309011
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: May 3, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
    Patent number: 5191224
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: March 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Semiconductor memory
    Patent number: 4928281
    Abstract: A semiconductor memory includes a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit, a parity check circuit for performing a parity check on storage data, at least one data unit at a time, input for both to and output from the memory array, and an external terminal for outputting the result of the parity check.
    Type: Grant
    Filed: June 10, 1987
    Date of Patent: May 22, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hinoko Kurosawa, Kazuya Itoh, Hisashi Nakamura, Masamichi Ishihara