Patents by Inventor Hiraku HASHIMOTO

Hiraku HASHIMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE USING DUAL WATER VAPOR FLOW OXIDATION AND APPARATUS FOR PERFORMING THE SAME
    Publication number: 20240121961
    Abstract: A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.
    Type: Application
    Filed: July 7, 2023
    Publication date: April 11, 2024
    Inventors: Hiraku HASHIMOTO, Eisuke TAKII, Shin KOYAMA
  • Three-dimensional memory device containing oxidation-resistant contact structures and methods of making the same
    Patent number: 11393757
    Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: July 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eisuke Takii, Hiraku Hashimoto, Shin Koyama
  • THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OXIDATION-RESISTANT CONTACT STRUCTURES AND METHODS OF MAKING THE SAME
    Publication number: 20220157724
    Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Inventors: Eisuke TAKII, Hiraku HASHIMOTO, Shin KOYAMA