Abstract: A power consumption of a plasma discharge cells arranged in columns and lines is reduced by, while applying a scan pulse to the cell lines sequentially, applying a high voltage pulse and a low voltage pulse to those of cell columns, which are connected to plasma display cells to be illuminated, prior to and after an initiation of gas discharge in those cells, respectively. Display signal including the high voltage pulse and the low voltage pulse is derived from a circuit comprising a first transistor, a second and third transistors having sources connected directly or through a diode to a drain of the first transistor, means for applying the high voltage to a drain of the second transistor and means for applying the low voltage to a drain of the third transistor, the second and third transistors being operated alternatively to provide the display signal at the drain of the first transistor.

Abstract: A high voltage signal producing circuit, such as a panel display driver, includes an input terminal receiving an input signal, a first signal processor receiving the input signal through a conductive line, a second signal processor receiving the input signal through a capacitor, at least one output stage in which P- and N-channel MOS output transistors are connected in series, one of the MOS output transistors receiving a signal from the first signal processor in response to the input signal and the other of the MOS output transistors receiving a signal from the second signal processor in response to the input signal, a high voltage power source energizing the output stage, a first low voltage power source energizing the first signal processor and a second low voltage power source energizing the second signal processor.

Abstract: Parasitic bipolar action is prevented in a high voltage MOSFET by a substrate contact region underlying the bottom of the source region and shorted to the source, to prevent forward bias of the source.

Abstract: An inverter circuit comprises a pair of N- and P-channel insulated gate field effect transistors coupled in series. One of the transistors is used as a load transistor and the other is used as a drive transistor. A diode is connected between the source and gate electrodes of the load transistor in order to hold the gate voltage of the load transistor. A resistor and a capacitor (having a larger capcitance than the gate capacitance of the load transistor) is connected to the gate electrode of the load transistor. In operation, a high voltage is applied to the source electrode of the load transistor. A low-voltage pulse, having a period shorter than the RC time constant of the resistor and capacitor, is applied through the capacitor to the gate electrode of the load transistor. The gate electrode of the drive transistor is supplied with a low-voltage input signal (having a phase which is the same as and not longer than the period of the pulse applied to the capacitor).

Abstract: An insulated gate field effect transistor is disclosed. The transistor comprises an insulator body, a semi-conductor layer of one conductivity type formed on a surface of the insulator body, a pair of source and drain regions of the opposite conductivity type formed in the semi-conductor layer along its one major surface and an extension region of the opposite conductivity type extending from one of the source and drain regions towards the remaining of the source and drain regions. A first insulating film is formed on the entire surface of the extension region, a gate insulating film is formed on a channel region of the transistor and a gate electrode is formed on the gate insulating film.