Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (N−1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.

Abstract: A clock control circuit includes a ring counter for outputting a signal of N bits count value and a complementary signal thereof; a rescue & flag generating circuit for effecting rescue from a bit pattern that is outside of expectations and generating a flag signal JBTFLG having a value corresponding to a combination of bits in a 2N-bit signal; a decoder; a clock selector for outputting a pair of clocks from multiphase clocks based upon a selection control signal from the decoder circuit; an interpolator for outputting a signal having a delay time corresponding to a time that is the result of internally dividing the phase difference between the pair of clocks; a phase comparator for comparing the phase of the interpolator output and the phase of a reference clock; and an interpolator control circuit, the shift direction of which varies, for outputting an interior-division ratio control signal that sets the interior-division ratio of the interpolator based upon the phase comparison by the phase comparator

Abstract: A clock control circuit includes a ring counter for outputting a signal of N bits count value and a complementary signal thereof; a rescue & flag generating circuit for effecting rescue from a bit pattern that is outside of expectations and generating a flag signal JBTFLG having a value corresponding to a combination of bits in a 2N-bit signal; a decoder; a clock selector for outputting a pair of clocks from multiphase clocks based upon a selection control signal from the decoder circuit; an interpolator for outputting a signal having a delay time corresponding to a time that is the result of internally dividing the phase difference between the pair of clocks; a phase comparator for comparing the phase of the interpolator output and the phase of a reference clock; and an interpolator control circuit, the shift direction of which varies, for outputting an interior-division ratio control signal that sets the interior-division ratio of the interpolator based upon the phase comparison by the phase comparator

Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (N−1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.