Patents by Inventor Hiro Kinoshita
Hiro Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121794Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.Type: GrantFiled: September 29, 2016Date of Patent: November 6, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Marika Gunji-Yoneoka, Atsushi Suyama, Jayavel Pachamuthu, Tsuyoshi Hada, Daewung Kang, Murshed Chowdhury, James Kai, Hiro Kinoshita, Tomoyuki Obu, Luckshitha Suriyasena Liyanage
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Patent number: 9985046Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.Type: GrantFiled: June 13, 2016Date of Patent: May 29, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Jixin Yu, Koji Miyata, Makoto Yoshida, Johann Alsmeier, Hiro Kinoshita, Daxin Mao
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Publication number: 20170365613Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.Type: ApplicationFiled: September 29, 2016Publication date: December 21, 2017Inventors: Marika GUNJI-YONEOKA, Atsushi SUYAMA, Jayavel PACHAMUTHU, Tsuyoshi HADA, Daewung KANG, Murshed CHOWDHURY, James KAI, Hiro KINOSHITA, Tomoyuki OBU, Luckshitha Suriyasena LIYANAGE
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Publication number: 20170358594Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: Zhenyu LU, Jixin YU, Koji MIYATA, Makoto YOSHIDA, Johann ALSMEIER, Hiro KINOSHITA, Daxin MAO
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Patent number: 9716101Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.Type: GrantFiled: October 30, 2015Date of Patent: July 25, 2017Assignee: SanDisk Technologies LLCInventors: Zhenyu Lu, Hiro Kinoshita, Daxin Mao, Johann Alsmeier, Wenguang Shi, Yingda Dong, Henry Chien, Kensuke Yamaguchi, Xiaolong Hu
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Publication number: 20160343718Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.Type: ApplicationFiled: October 30, 2015Publication date: November 24, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Zhenyu Lu, Hiro Kinoshita, Daxin Mao, Johann Alsmeier, Wenguang Shi, Yingda Dong, Henry Chien, Kensuke Yamaguchi, Xiaolong Hu
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Patent number: 9455352Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: December 17, 2013Date of Patent: September 27, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Patent number: 9245895Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: July 26, 2011Date of Patent: January 26, 2016Assignee: Cypress Semiconductor CorporationInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 9224475Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.Type: GrantFiled: August 23, 2012Date of Patent: December 29, 2015Assignee: SanDisk Technologies Inc.Inventors: Jongsun Sel, Tuan Pham, Kazuya Tokunaga, Hiro Kinoshita
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Publication number: 20140167138Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicant: SPANSION LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Publication number: 20140054669Abstract: A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Inventors: Jongsun Sel, Tuan Pham, Kazuya Tokunaga, Hiro Kinoshita
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Patent number: 8653581Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: December 22, 2008Date of Patent: February 18, 2014Assignee: Spansion LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui
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Patent number: 8330209Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: March 23, 2011Date of Patent: December 11, 2012Assignee: Spansion LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi
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Publication number: 20110278660Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: ApplicationFiled: July 26, 2011Publication date: November 17, 2011Applicant: SPANSION LLCInventors: Ning Cheng, K.T. Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Patent number: 8012830Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.Type: GrantFiled: August 8, 2007Date of Patent: September 6, 2011Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue, Chungho Lee, Minghao Shen, Angela Hui, Huaqiang Wu
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Publication number: 20110169069Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: ApplicationFiled: March 23, 2011Publication date: July 14, 2011Applicant: SPANSION, LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi
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Patent number: 7943983Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.Type: GrantFiled: December 22, 2008Date of Patent: May 17, 2011Assignee: Spansion LLCInventors: Huaqiang Wu, Hiro Kinoshita, Ning Cheng, Arturo Ruiz, Jihwan Choi
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Patent number: 7935596Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.Type: GrantFiled: December 22, 2008Date of Patent: May 3, 2011Assignee: Spansion LLCInventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi
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Patent number: 7906807Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: GrantFiled: June 30, 2010Date of Patent: March 15, 2011Assignee: Spansion LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, Kuo-Tung Chang, Huaqiang Wu
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Publication number: 20100264480Abstract: Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: SPANSION LLCInventors: Ning Cheng, Calvin Gabriel, Angela Hui, Lei Xue, Harpreet Kaur Sachar, Phillip Lawrence Jones, Hiro Kinoshita, K.T Chang, Huaqiang Wu