Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Abstract: A photoelectric conversion device according to an embodiment of the present disclosure includes: a first semiconductor layer in which a transfer transistor is provided; a second semiconductor layer in which a pixel transistor is provided; and a wiring layer in which a gate wiring line coupled to a gate of the transfer transistor is provided. A portion or all of the pixel transistor is disposed, in plan view, in a region between a first gate wiring line and a second gate wiring line. The first gate wiring line is coupled to the gate of the transfer transistor in one of two pixels adjacent to each other. The second gate wiring line is coupled to the gate of the transfer transistor in another of the two pixels adjacent to each other.

Abstract: The purpose of the present technology is to improve photoelectric conversion efficiency. A first semiconductor layer, a second semiconductor layer on a side of the first semiconductor layer remote from a light incident surface, a photoelectric conversion part in the first semiconductor layer, a charge holding region in the first semiconductor layer and configured to accumulate a signal charge generated by photoelectric conversion performed by the photoelectric conversion part, first and second field effect transistors each including a gate electrode and a pair of main electrode regions, each of the pairs of main electrode regions being provided in the second semiconductor layer, and a contact electrode extending through the first and second semiconductor layers and directly connected to any one of the pair of main electrode regions of the first field effect transistor, the gate electrode of the second field effect transistor, and the charge holding region are included.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device includes a photodiode as a photoelectric conversion unit, a transfer gate that reads out charges from the photodiode, a floating diffusion from which the charges of the photodiode are read by an operation of the transfer gate, and an amplifying transistor connected to the floating diffusion. More particularly, the amplifying transistor is of a fully-depleted type. Such an amplifying transistor includes an amplifier gate (gate electrode) extending in a direction perpendicular to convex strips formed by processing a surface layer of a semiconductor layer, for example.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.

Abstract: The present technology relates to a solid-state image pickup apparatus and electronic equipment that makes it possible to suppress read noise. A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.

Abstract: A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.

Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.

Abstract: A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.

Abstract: Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.