Patents by Inventor Hiroaki Aotsu
Hiroaki Aotsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6643189Abstract: A memory device which includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data, and a controller having a first data input connected to receive first data, a second data input connected to receive second data, a third data input connected to receive a function mode signal, and operation unit for executing operations between the first data and the second data. The operation unit includes a function setting unit for setting a function indicated by a function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the set function is executed for the first and second data. The operation result is written into the selected part of the storage locations during one memory cycle.Type: GrantFiled: January 31, 2002Date of Patent: November 4, 2003Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 6552730Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.Type: GrantFiled: May 8, 1995Date of Patent: April 22, 2003Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Kiichiro Urabe
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Patent number: 6437790Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.Type: GrantFiled: June 7, 1995Date of Patent: August 20, 2002Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Kiichiro Urabe
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Publication number: 20020093852Abstract: A memory device which includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data, and a controller having a first data input connected to receive first data, a second data input connected to receive second data, a third data input connected to receive a function mode signal, and operation unit for executing operations between the first data and the second data. The operation unit includes a function setting unit for setting a function indicated by a function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the set function is executed for the first and second data. The operation result is written into the selected part of the storage locations during one memory cycle.Type: ApplicationFiled: January 31, 2002Publication date: July 18, 2002Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 6359812Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: December 29, 2000Date of Patent: March 19, 2002Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Publication number: 20010046160Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: ApplicationFiled: December 29, 2000Publication date: November 29, 2001Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 6198665Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: October 28, 1999Date of Patent: March 6, 2001Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 6028795Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: May 3, 1999Date of Patent: February 22, 2000Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5923591Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: April 5, 1998Date of Patent: July 13, 1999Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5838337Abstract: A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal.Type: GrantFiled: August 23, 1994Date of Patent: November 17, 1998Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5781479Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: May 9, 1997Date of Patent: July 14, 1998Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5767864Abstract: A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.Type: GrantFiled: August 23, 1994Date of Patent: June 16, 1998Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5719809Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: August 9, 1996Date of Patent: February 17, 1998Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5617360Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: January 18, 1996Date of Patent: April 1, 1997Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5615155Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: January 4, 1996Date of Patent: March 25, 1997Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5592649Abstract: A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. utilizing presetting in a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.Type: GrantFiled: July 26, 1994Date of Patent: January 7, 1997Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara
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Patent number: 5548744Abstract: In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.Type: GrantFiled: December 12, 1994Date of Patent: August 20, 1996Assignee: Hitachi, Ltd.Inventors: Toshihiko Ogura, Hiroaki Aotsu, Koichi Kimura, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5523973Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: June 2, 1995Date of Patent: June 4, 1996Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5499222Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: May 5, 1995Date of Patent: March 12, 1996Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda
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Patent number: 5493528Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.Type: GrantFiled: May 5, 1995Date of Patent: February 20, 1996Assignee: Hitachi, Ltd.Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Mitsuru Ikegami, Tadashi Kuwabara, Hiromichi Enomoto, Tadashi Kyoda