Patents by Inventor Hiroaki ASHIDATE

Hiroaki ASHIDATE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250029956
    Abstract: A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 23, 2025
    Inventors: Yasunori IWASHITA, Hisashi KATO, Hiroaki ASHIDATE, Masayoshi TAGAMI
  • Publication number: 20240324195
    Abstract: A semiconductor device manufacturing method of embodiments includes: forming an insulating film on an outer peripheral portion of a surface of a first substrate; after forming the insulating film, forming a silicon layer in contact with the surface inside the insulating film; and forming a porous silicon layer by making the silicon layer inside the insulating film porous using an anodization method.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 26, 2024
    Applicant: Kioxia Corporation
    Inventors: Hakuba KITAGAWA, Mariko SUMIYA, Kohei NAKAMURA, Hiroaki ASHIDATE, Jun TAKAGI, Masayuki FUKUMOTO
  • Publication number: 20230411344
    Abstract: In a method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate to a first principal surface, on which the first structure is formed, of the first substrate. The supporting substrate is higher in rigidity than the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The third substrate is removed from the second bonded body.
    Type: Application
    Filed: February 28, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Tomoyuki TAKEISHI
  • Publication number: 20230411322
    Abstract: A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body.
    Type: Application
    Filed: February 28, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Tomoyuki TAKEISHI
  • Publication number: 20230397425
    Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cell array layers. Each of the plurality of the memory cell array layers includes a plurality of memory cells. Each of the plurality of the memory cells includes a multi-layered body. The multi-layered body has a staircase structure including an inclined portion. The multi-layered body has a plurality of electrode layers having a plurality of end portions. The positions of the plurality of the end portions are displaced from each other for each stacked position in the staircase structure. Two memory cell array layers adjacent to each other have a multi-layered boundary surface therebetween. The inclined portion of each of the two memory cell array layers adjacent to each other faces the multi-layered boundary surface.
    Type: Application
    Filed: March 13, 2023
    Publication date: December 7, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Tomoyuki TAKEISHI
  • Publication number: 20230395499
    Abstract: In one embodiment, a semiconductor device includes a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, disposed on the first pad, and being in contact with the first pad. The device further includes a third pad provided in the second insulator, and disposed above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, disposed on the third pad, and being in contact with the third pad. Furthermore, a shape of the third or fourth pad is different from a shape of the first or second pad.
    Type: Application
    Filed: March 8, 2023
    Publication date: December 7, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Hisashi KATO, Tomoyuki TAKEISHI
  • Publication number: 20230395498
    Abstract: A semiconductor storage device includes a first layer including a first surface and a second surface located opposite to the first surface. The first layer includes a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells. A second layer includes a third surface and a fourth surface located opposite to the third surface. The second layer includes a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells. The first layer and the second layer are joined together on the first surface and the third surface.
    Type: Application
    Filed: March 3, 2023
    Publication date: December 7, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroaki ASHIDATE, Tomoyuki TAKEISHI
  • Publication number: 20230307361
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Yasunori IWASHITA, Shinya ARAI, Keisuke NAKATSUKA, Hiroaki ASHIDATE
  • Publication number: 20230307396
    Abstract: A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Yasunori IWASHITA, Shinya ARAI, Keisuke NAKATSUKA, Hiroaki ASHIDATE
  • Publication number: 20230197672
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a magnification difference acquirer configured to acquire a value of difference in magnification between a first substrate and a second substrate. The apparatus further includes a deformation amount determiner configured to determine a value of deformation amount of a chuck that holds the first or second substrate, based on the value of the difference in magnification. The apparatus further includes a gap determiner configured to determine a value of a gap between the first substrate and the second substrate, based on the value of the deformation amount. The apparatus further includes a bonding controller configured to control the deformation amount to the determined value and control the gap to the determined value, before the first substrate and the second substrate are bonded together.
    Type: Application
    Filed: September 9, 2022
    Publication date: June 22, 2023
    Applicant: Kioxia Corporation
    Inventors: Ai MORI, Hiroaki ASHIDATE
  • Publication number: 20210398825
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a substrate holder configured to hold a plurality of substrates such that the substrates are arranged in parallel to each other. The apparatus further includes a fluid injector including a plurality of openings that inject fluid to areas in which distances from surfaces of the substrates are within distances between centers of the substrates adjacent to each other, the fluid injector being configured to change injection directions of the fluid injected from the openings in planes that are parallel to the surfaces of the substrates by self-oscillation.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomohiko SUGITA, Katsuhiro SATO, Hiroaki ASHIDATE
  • Publication number: 20210265181
    Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshinori KITAMURA, Katsuhiro SATO, Hiroaki ASHIDATE
  • Publication number: 20200295027
    Abstract: A semiconductor storage device includes a first stacked body, a second stacked body, a first division film, a second division film, and a plurality of discrete films. The a first stacked body includes first electrode layers stacked in a first direction. The second stacked body, above the first stacked body, includes second electrode layers stacked in the first direction. The second semiconductor layer is electrically connected to the first semiconductor layer. The first division film, extending in the first direction through the first stacked body, divides the first stacked body in a second direction crossing the first direction. The second division film, extending in the first direction through the second stacked body, divides the second stacked body in the second direction. The discrete films, extending in the first direction through the second stacked body, are disposed above the first division film.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi SAKATA, Kazutaka SUZUKI, Hiroaki ASHIDATE, Katsuhiro SATO, Satoshi NAKAOKA
  • Publication number: 20200273726
    Abstract: A substrate treatment apparatus according to an embodiment includes a treatment tank, a container, a measuring instrument, and a controller. The treatment tank stores a chemical solution to treat a substrate. The container contains a liquid including ammonia from which a gas discharged from the treatment tank is gas-liquid separated. The measuring instrument measures an amount of the ammonia included in the liquid over time. The controller controls the treatment of the substrate based on the amount of the ammonia.
    Type: Application
    Filed: August 22, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAKAOKA, Katsuhiro SATO, Hiroaki ASHIDATE, Shinsuke MURAKI, Yuji HASHIMOTO
  • Publication number: 20180233383
    Abstract: According to an embodiment, a substrate treatment apparatus includes a tank and a control mechanism. The tank houses a substrate including a silicon oxide film and a silicon nitride film, and receives a supply of a phosphoric acid solution capable of selectively etching the silicon nitride film rather than the silicon oxide film. The control mechanism controls an etching state of the silicon nitride film in the tank, by alternately switching two modes based on preset time allocation. The two modes include a first mode in which a first phosphoric acid solution is contact with the substrate and a second mode in which a second phosphoric acid solution with a selection ratio of the silicon nitride film to the silicon oxide film different from that of the first phosphoric acid solution, is contact with the substrate.
    Type: Application
    Filed: September 13, 2017
    Publication date: August 16, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroaki ASHIDATE, Hiroyasu Iimori, Katsuhiro Sato
  • Publication number: 20180082862
    Abstract: A substrate processing device includes a bath configured to accommodate a plurality of substrates and configured to store a liquid for etching the plurality of substrates, a plurality of bubble generators configured to generate bubbles in the liquid, the bubble generators provided so as to correspond to each of the plurality of substrates, a measurement device configured to measure the generation state of the bubbles of at least one of the plurality of bubble generators, and a control device configured to individually control at least one of the plurality of bubble generators based on the measurement result of the measurement device.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 22, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroaki ASHIDATE, Katsuhiro SATO
  • Publication number: 20170309501
    Abstract: According to embodiments, a substrate treatment apparatus includes a housing, a heater and a pipe. The housing stores solution containing phosphoric acid and houses a substrate including a silicon substrate. The heater heats the solution over a normal boiling point of the solution. The pipe supplies heated solution heated by the heater into the housing while generating air bubbles.
    Type: Application
    Filed: September 1, 2016
    Publication date: October 26, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshinori KITAMURA, Katsuhiro SATO, Hiroaki ASHIDATE
  • Publication number: 20170243910
    Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki ASHIDATE, Kazumasa TANIDA
  • Publication number: 20160126136
    Abstract: A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki ASHIDATE, Kazumasa TANIDA
  • Publication number: 20160035766
    Abstract: A semiconductor device such as, for example an imaging sensor, includes a semiconductor layer in which, for example, a photodiode may be formed. An insulation film is disposed on a surface of the semiconductor layer. The insulation film includes one or more wirings or wiring layers formed therein. A semiconductor support substrate is disposed on the insulation film. The semiconductor support substrate includes a first layer (or region) and a second layer (or region) that is between the insulation film and the first layer. The first layer has a bulk micro defect density that is higher than a bulk micro defect density of the second layer.
    Type: Application
    Filed: February 17, 2015
    Publication date: February 4, 2016
    Inventors: Satoshi HONGO, Tsuyoshi MATSUMURA, Hiroaki ASHIDATE, Kazumasa TANIDA