Abstract: A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two operands to 6 for a third result; a fourth circuit adding the two operands to 1 for a fourth result; a fifth circuit adding the two operands to 11 for a fifth result; a sixth circuit adding the two operands to 7 for a sixth result; and a selection circuit selecting the first, second, fourth or fifth result when adding two numbers of identical signs or adding two numbers of different signs resulting in a non-negative result, and selecting a 1's complement of the first, third, fourth or sixth result when adding two numbers of different signs resulting in a negative result.

Abstract: In a parity prediction circuit which corrects the predicted parity using AND/OR parity inversion condition generation circuits, predicted parity and inversion conditions are corrected using an EOR condition of one of data buses. Two parity prediction logics are sufficient; the added correction logic circuit requires only the EOR condition for one data bus, and the hardware configuration can be reduced. Further, control signals from opcode signals are employed in the latter half of the logic operations, and thereby parity prediction is possible at high speed comparable with circuits which have parity prediction logic for each instruction.

Abstract: A processor including a plurality of computation circuit blocks each having a function to perform a computation for each of a plurality of pieces of divided data to be computed, and a function to power on/off each power supply includes a signal value fixing circuit, which is provided for each of the computation circuit blocks, for fixing one or both of signal values of an input and an output of each of the computation circuit blocks, and a power supply control sequencer circuit for instructing each signal value fixing circuit to fix the signal value or to release the signal value from being fixed, and for respectively instructing the computation circuit blocks to power on/off each power supply in a step-by-step manner on the basis of a power supply control signal provided from an instruction controlling circuit for controlling an input of a computation instruction to the processor.

Abstract: In a parity prediction circuit which corrects the predicted parity using AND/OR parity inversion condition generation circuits, predicted parity and inversion conditions are corrected using an EOR condition of one of data buses. Two parity prediction logics are sufficient; the added correction logic circuit requires only the EOR condition for one data bus, and the hardware configuration can be reduced. Further, control signals from opcode signals are employed in the latter half of the logic operations, and thereby parity prediction is possible at high speed comparable with circuits which have parity prediction logic for each instruction.

Abstract: A sound signal recorded in a memory synchronously with a low-frequency clock signal is read out with the low-frequency clock signal to reproduce a normal sound, thereby enabling checking of the sound signal recorded in the memory. For recording in a recording medium, the sound signal is read out with a high-frequency clock signal to effect time axis compression. By designating an address to start writing, a sound signal can be written starting with any address thereby facilitating editing. An analog sound signal previously recorded on a magnetic recording medium is time axis expanded by a time axis expansion device and then outputted from a sound output device, and the analog sound signal is hybridized with another analog sound signal inputted from a microphone, time axis compressed by a time axis conversion device, and recorded on the magnetic recording device.