Abstract: An output circuit used in a common driver for a flat panel electronic display device includes "n" two-input OR circuits of a CMOS circuit structure, where "n" is a positive integer corresponding to the number of a row electrodes of a flat panel display. One input of each of the OR circuits is connected to a corresponding bit of an n-bit shifter register, and an output of the OR circuits is connected to a corresponding one of the row electrodes of the flat panel display so as to drive the corresponding electrode. A control signal is connected directly to the other input of the first OR circuit and a first one of "n-1" cascaded non-inverting buffers. Outputs of these cascaded non-inverting buffers are connected to the other input of the remaining OR circuits, respectively.

Abstract: A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit component is shifted to a higher order bit every half of the period of a clock signal so that a shifting speed thereof can be made two times faster than that in a conventional shift register circuit. It may be arranged such that a higher order bit section starts to output a signal after the preceding lower order bit section outputs a low level signal thereby enabling to avoid the signals outputted by the bit sections neighboring to each other becoming simultaneously intermediate values between a high level and a low level. Also, the bit sections may be cascade-connected such that each of the sections takes a logical operation of the input and output signals of the latch portion. In view of the configuration involved, the number of elements per bit can be reduced.