Patents by Inventor Hiroaki Furihata

Hiroaki Furihata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754863
    Abstract: The semiconductor device improves heat dissipation by loading a diode and a MOSFET or IGBT in a single package. A drain electrode disposed on a rear surface of a MOSFET chip is soldered to an upper surface of a first lead frame, and a cathode electrode disposed on a rear surface of a diode chip is soldered to an upper surface of a second lead frame. Rear surfaces of the first lead frame and second lead frame to which neither the diode chip nor the MOSFET chip is connected are disposed so as to be exposed from a sealing resin.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 5, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Sota Watanabe, Hiroaki Furihata, Makoto Imai
  • Publication number: 20100045982
    Abstract: A particle counting device 11 for detecting and counting particles in a fluid to be measured comprises a measuring section 13 for detecting particles and a control section 12 for processing the output signal from the measuring section 13. When an abnormality occurs, a signal to issue a warning is generated. With this, a constant monitoring or observation is possible. Also, a particle counting system comprising a plurality of particle counting devices 11 and an information processing device 17 for processing the results of the counting by the particle processing devices 11 is also provided. The plurality of particle counting devices 11 are electrically connected to the information processing device 17 in multiple and in parallel. Alternately, a particle counting system comprising a plurality of particle counting devices 11 for detecting and counting particles in a fluid to be measured is also provided.
    Type: Application
    Filed: November 28, 2006
    Publication date: February 25, 2010
    Applicant: NIDEC SANKYO CORPORATION
    Inventors: Haruhiro Tsuneta, Eiichi Sugioka, Hiroshi Tonouchi, Junichi Shiozawa, Kenichi Hayashi, Tetsuo Momose, Hiroaki Furihata
  • Patent number: 7495927
    Abstract: A mounting structure includes a base member and an electronic component having a protruded electrode which is formed on a transparent substrate. The electrode includes pads and elastic projections that are covered with a conductive film. On the transparent substrate, terminals connected to the conductive film are formed. Dummy projections are provided on the surface of the base member. When mounting the electronic component, the electrodes are deformed by the pressure for the mounting. The dummy projections formed on the base member are also deformed. A pattern, for visually inspecting the deformation volume of dummy projections, is marked on the transparent substrate.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: February 24, 2009
    Assignee: Epson Imaging Devices Corporation
    Inventors: Hiroaki Furihata, Hiroyuki Onodera
  • Publication number: 20080174979
    Abstract: A mounting structure includes a base member and an electronic component having a protruded electrode which is formed on a transparent substrate. The electrode includes pads and elastic projections that are covered with a conductive film. On the transparent substrate, terminals connected to the conductive film are formed. Dummy projections are provided on the surface of the base member. When mounting the electronic component, the electrodes are deformed by the pressure for the mounting. The dummy projections formed on the base member are also deformed. A pattern, for visually inspecting the deformation volume of dummy projections, is marked on the transparent substrate.
    Type: Application
    Filed: December 14, 2007
    Publication date: July 24, 2008
    Applicant: EPSON IMAGING DEVICES CORPORATION
    Inventors: Hiroaki Furihata, Hiroyuki Onodera
  • Patent number: 7268416
    Abstract: A mounting structure includes a mounting substrate on which a plurality of mounting pads each constituting a portion of a conductive pattern extending in a Y direction are arranged in an X direction, the X direction and the Y direction being two directions orthogonal to each other, and a member that is mounted on the mounting substrate so as to be electrically connected to the mounting pads. In the mounting structure, a first conductive layer, an insulating layer, a second conductive layer, and a third conductive layer are formed on the mounting substrate in this order from a lower side to an upper side.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: September 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Furihata
  • Publication number: 20050248012
    Abstract: A mounting structure includes a mounting substrate on which a plurality of mounting pads each constituting a portion of a conductive pattern extending in a Y direction are arranged in an X direction, the X direction and the Y direction being two directions orthogonal to each other, and a member that is mounted on the mounting substrate so as to be electrically connected to the mounting pads. In the mounting structure, a first conductive layer, an insulating layer, a second conductive layer, and a third conductive layer are formed on the mounting substrate in this order from a lower side to an upper side.
    Type: Application
    Filed: May 5, 2005
    Publication date: November 10, 2005
    Inventor: Hiroaki Furihata
  • Publication number: 20050051908
    Abstract: A diode exhibiting a high reverse breakdown voltage is manufactured by employing a flame-resisting epoxy resin, the extract of which when extracted under predetermined conditions exhibits electrical conductivity of 250 ?S/cm or lower. According to the invention, sealant resins for high-voltage diodes with excellent moisture resistance are selected by employing the electrical resistance value found to be appropriate for a reference value not by assembling a high-voltage diode, but rather by conducting the predetermined humidity resistance test on the sealant resins. The sealant resin selection according to the invention facilitates reducing the resin costs, and, therefore, manufacturing high-voltage diodes exhibiting excellent humidity resistance with low manufacturing costs.
    Type: Application
    Filed: July 26, 2004
    Publication date: March 10, 2005
    Inventors: Masaki Ichinose, Akira Amano, Hideaki Ito, Hiroaki Furihata
  • Patent number: 6506978
    Abstract: A flexible wiring board 100 includes a first single-sided flexible board 10 and a second single-sided flexible board 20. The first single-sided flexible board 10 includes a first base body 12 having an insulative property, and a first wiring layer 14 formed in a predetermined pattern on the first base body. The second single-sided flexible board 20 includes a second base body 22 having an insulative property, and a second wiring layer 24 formed in a predetermined pattern on the second base body. The first and second single-sided flexible boards respectively have insulating layers 16 and 26 covering the wiring layers 14 and 24, and the insulating layers are provided with contact sections C10 and C20. The first single-sided flexible board 10 and the second single-sided flexible board 20 are arranged so that the first wiring layer and the second wiring layer face each other, and are bonded through an anisotropically conductive adhesive layer 30.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: January 14, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Furihata
  • Publication number: 20010045624
    Abstract: A plurality of optimized diode chips are connected in series with each other to provide a high-voltage silicon diode rectifying device. Each chip has an improved withstand voltage and inverse surge resistance which improves the overall usefulness and efficiency of high-voltage silicon diodes. This invention also reduces costs by requiring fewer individual diode chips. The specific resistance of the (n)-type silicon substrate is in a critical range of between 20 to 50 &OHgr;cm. The diffusion depth of the p+ anode layer is in a critical range of between 30 to 200 &mgr;m. The thickness of the n− base layer is 0.54×(&rgr;·Vsr)½ or greater. In another embodiment, the specific resistance of the silicon substrate is in the range of 32 to 40 &OHgr;cm, and diffusion depth of the p+ anode layer is in the range of 70 to 200 &mgr;m. In yet another embodiment, a cathode layer is diffused on the semiconductor base material.
    Type: Application
    Filed: February 3, 1999
    Publication date: November 29, 2001
    Inventors: NORIYUKI IWAMURO, MICHIO NEMOTO, HIROAKI FURIHATA, TAKAHIRO KUBOYAMA