Patents by Inventor Hiroaki HARUNA

Hiroaki HARUNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power semiconductor device and substrate with dimple region
    Patent number: 11842968
    Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: December 12, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Yabuta, Takayuki Yamada, Yuya Muramatsu, Noriyuki Besshi, Yutaro Sugi, Hiroaki Haruna, Masaru Fuku, Atsuki Fujita
  • POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE
    Publication number: 20220254738
    Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei YABUTA, Takayuki YAMADA, Yuya MURAMATSU, Noriyuki BESSHI, Yutaro SUGI, Hiroaki HARUNA, Masaru FUKU, Atsuki FUJITA
  • Power semiconductor device and manufacturing method for power semiconductor device
    Patent number: 11342281
    Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 24, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei Yabuta, Takayuki Yamada, Yuya Muramatsu, Noriyuki Besshi, Yutaro Sugi, Hiroaki Haruna, Masaru Fuku, Atsuki Fujita
  • POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE
    Publication number: 20200251423
    Abstract: A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.
    Type: Application
    Filed: October 25, 2018
    Publication date: August 6, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kohei YABUTA, Takayuki YAMADA, Yuya MURAMATSU, Noriyuki BESSHI, Yutaro SUGI, Hiroaki HARUNA, Masaru FUKU, Atsuki FUJITA