Patents by Inventor Hiroaki Himi
Hiroaki Himi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7838909Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.Type: GrantFiled: September 28, 2006Date of Patent: November 23, 2010Assignee: Denso CorporationInventors: Hiroaki Himi, Takashi Nakano, Shoji Mizuno
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Patent number: 7754580Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: April 12, 2007Date of Patent: July 13, 2010Assignee: DENSO CORPORATIONInventors: Hiroaki Himi, Noriyuki Iwamori
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Publication number: 20080099862Abstract: A method for manufacturing a physical quantity sensor includes: forming a sensor element in a first wafer; stacking a support substrate, a connection layer and a cap layer in this order so that a second wafer is prepared; bonding the cap layer of the second wafer to the first wafer in such a manner that the sensor element is disposed in a space between the first wafer and the second wafer; removing the support substrate and the connection layer from the second wafer; and dividing the first wafer together with the cap layer into a plurality of chips so that a plurality of physical quantity sensors is formed.Type: ApplicationFiled: September 27, 2007Publication date: May 1, 2008Applicant: DENSO CORPORATIONInventors: Tetsuo Fujii, Hiroaki Himi
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Publication number: 20070194413Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: ApplicationFiled: April 12, 2007Publication date: August 23, 2007Applicant: DENSO CORPORATIONInventors: Hiroaki Himi, Noriyuki Iwamori
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Patent number: 7239181Abstract: A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance elements are successively connected to one another in series between the GND potential and the predetermined potential. A resistance or capacitance element at the GND potential side is a first stage and a resistance or capacitance element at the predetermined potential side is an n-th stage. Gate terminals of the transistor elements at the respective stages excluding the transistor element at the first stage are successively connected to connection points. An output is taken from the terminal at the predetermined potential side of the transistor element of the n-th stage.Type: GrantFiled: October 20, 2005Date of Patent: July 3, 2007Assignee: DENSO CorporationInventors: Hiroaki Himi, Akira Yamada, Takeshi Kuzuhara
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Patent number: 7220654Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: November 20, 2003Date of Patent: May 22, 2007Assignee: Denso CorporationInventors: Hiroaki Himi, Noriyuki Iwamori
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Publication number: 20070018275Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.Type: ApplicationFiled: September 28, 2006Publication date: January 25, 2007Applicant: DENSO CORPORATIONInventors: Hiroaki Himi, Takashi Nakano, Shoji Mizuno
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Patent number: 7132347Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.Type: GrantFiled: September 8, 2003Date of Patent: November 7, 2006Assignee: Denso CorporationInventors: Hiroaki Himi, Takashi Nakano, Shoji Mizuno
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Publication number: 20060231868Abstract: A semiconductor device includes: a plurality of transistors connected in series between a ground potential and a predetermined potential; an input terminal provided by a gate terminal of the first step transistor; a plurality of resistors connected in series between the ground potential and the predetermined potential; and an output terminal provided by a predetermined potential side terminal of the Nth step transistor. A gate terminal of each transistor other than the first step transistor is sequentially connected between neighboring two resistors. One of the resistors defined as an Ith step resistor has a resistance, which is smaller than a resistance of a (I+1)th step resistor.Type: ApplicationFiled: April 18, 2006Publication date: October 19, 2006Applicant: DENSO CORPORATIONInventors: Akira Yamada, Hiroaki Himi, Nozomu Akagi, Junichi Nagata
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Publication number: 20060087343Abstract: A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance elements are successively connected to one another in series between the GND potential and the predetermined potential. A resistance or capacitance element at the GND potential side is a first stage and a resistance or capacitance element at the predetermined potential side is an n-th stage. Gate terminals of the transistor elements at the respective stages excluding the transistor element at the first stage are successively connected to connection points. An output is taken from the terminal at the predetermined potential side of the transistor element of the n-th stage.Type: ApplicationFiled: October 20, 2005Publication date: April 27, 2006Applicant: DENSO CORPORATIONInventors: Hiroaki Himi, Akira Yamada, Takeshi Kuzuhara
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Patent number: 6768183Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: GrantFiled: April 19, 2002Date of Patent: July 27, 2004Assignee: Denso CorporationInventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
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Publication number: 20040108566Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: ApplicationFiled: November 20, 2003Publication date: June 10, 2004Inventors: Hiroaki Himi, Noriyuki Iwamori
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Publication number: 20040046226Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.Type: ApplicationFiled: September 8, 2003Publication date: March 11, 2004Inventors: Hiroaki Himi, Takashi Nakano, Shoji Mizuno
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Patent number: 6676748Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.Type: GrantFiled: November 16, 2000Date of Patent: January 13, 2004Assignee: Denso CorporationInventors: Hiroaki Himi, Noriyuki Iwamori
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Patent number: 6573144Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: GrantFiled: August 2, 2002Date of Patent: June 3, 2003Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
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Publication number: 20020190309Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: ApplicationFiled: August 2, 2002Publication date: December 19, 2002Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
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Publication number: 20020153592Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: ApplicationFiled: April 19, 2002Publication date: October 24, 2002Inventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
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Patent number: 6465839Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: GrantFiled: April 6, 2001Date of Patent: October 15, 2002Assignee: Denso CorporationInventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
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Publication number: 20020005550Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+-type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: ApplicationFiled: April 6, 2001Publication date: January 17, 2002Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
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Patent number: 6064158Abstract: A scan driver IC for an EL element in an EL display device supplies, in a positive field, a positive polarity scan voltage and an offset voltage which is higher than ground to scan side driver ICs from voltage supply circuits, and the scan side driver ICs set voltage of scan electrodes to be the offset voltage in the positive field, together with outputting the positive polarity scan voltage to the scan electrodes during electroluminescence timing. Consequently, a voltage of Vr-Vm is applied to the scan side driver ICs, and so the breakdown voltage can be lowered by an amount corresponding to the offset voltage Vm. Circuits for providing such voltages, for providing alternating current drive voltages, and for reducing power consumption of the drive circuits are also disclosed.Type: GrantFiled: December 3, 1998Date of Patent: May 16, 2000Assignee: Denso CorporationInventors: Hiroyuki Kishita, Masahiko Osada, Hiroaki Himi