Abstract: According to one embodiment, there is provided a semiconductor device including a first switch, a first capacitive element, a second capacitive element, a first rectifying circuit, a second rectifying circuit, a third rectifying circuit, and a fourth rectifying circuit. The first switch is electrically inserted between a first node and a second node. The first capacitive element is electrically inserted between a first signal node and the first node. The second capacitive element is electrically inserted between a second signal node and the second node. The first rectifying circuit is electrically connected to the first node with a first polarity. The second rectifying circuit is electrically connected to the first node with a second polarity opposite to the first polarity. The third rectifying circuit is electrically connected to the second node with the first polarity. The fourth rectifying circuit is electrically connected to the second node with the second polarity.

Abstract: According to an embodiment, a voltage-controlled oscillator has a variable capacitive element with a capacitance that is changed by a voltage to be applied thereto. One electrode of the variable capacitive element is connected to a control input terminal where a control voltage that controls an oscillation frequency is applied thereto. It has a compensation voltage generation circuit that generates a voltage that changes with a temperature thereof. It has a resistive element with one end that is directly connected to another electrode of the variable capacitive element and another end that is supplied with an output voltage of the compensation voltage generation circuit.

Abstract: According to one embodiment, there is provided a semiconductor device including a first switch, a first capacitive element, a second capacitive element, a first rectifying circuit, a second. rectifying circuit, a third rectifying circuit, and a fourth rectifying circuit. The first switch is electrically inserted between a first node and a second node. The first capacitive element is electrically inserted between a first signal node and the first node. The second capacitive element is electrically inserted between a second signal node and the second node. The first rectifying circuit is electrically connected to the first node with a first polarity. The second rectifying circuit is electrically connected to the first node with a second polarity opposite to the first polarity. The third rectifying circuit is electrically connected to the second node with the first polarity. The fourth rectifying circuit is electrically connected to the second node with the second polarity.

Abstract: According to an embodiment, a voltage-controlled oscillator has a variable capacitive element with a capacitance that is changed by a voltage to be applied thereto. One electrode of the variable capacitive element is connected to a control input terminal where a control voltage that controls an oscillation frequency is applied thereto. It has a compensation voltage generation circuit that generates a voltage that changes with a temperature thereof. It has a resistive element with one end that is directly connected to another electrode of the variable capacitive element and another end that is supplied with an output voltage of the compensation voltage generation circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit device includes an oscillator, a frequency divider, and a control circuit. The oscillator is configured to oscillate at a variable oscillation frequency. The frequency divider is configured to oscillate at a variable free-running oscillation frequency, and has a frequency dividing range that transitions according to a variation in the free-running oscillation frequency. The control circuit is configured to control the oscillator to vary the oscillation frequency during a calibration operation that adjusts the oscillation frequency and is configured to control the frequency divider to cause the frequency dividing range to transition based on an amount of variation of the oscillation frequency.

Abstract: According to some embodiments, there is provided a signal generating device, including a signal generator and a local signal generating unit. The signal generator generates a signal of a fixed frequency. The local signal generating unit generates, based on the signal of the fixed frequency, a first local signal to convert a frequency of a first signal, and a second local signal to convert a frequency of a second signal. The second signal is a signal resulting from that the first signal is subjected to frequency conversion based on the first local signal and has a frequency different from the first local signal.

Abstract: According to some embodiments, there is provided a signal generating device, including a signal generator and a local signal generating unit. The signal generator generates a signal of a fixed frequency. The local signal generating unit generates, based on the signal of the fixed frequency, a first local signal to convert a frequency of a first signal, and a second local signal to convert a frequency of a second signal. The second signal is a signal resulting from that the first signal is subjected to frequency conversion based on the first local signal and has a frequency different from the first local signal.

Abstract: A frequency converter includes a first pair of transistors including first and second transistors, a second pair of transistors including third and fourth transistors, and a variable impedance circuit. The first transistor includes source terminal being connected to positive-phase input terminal, drain terminal being connected to positive-phase output terminal, and gate terminal being supplied with positive-phase local signal. The second transistor includes source terminal being connected to positive-phase input terminal, drain terminal being connected to negative-phase output terminal, and gate terminal being supplied with negative-phase local signal. The third transistor includes source terminal being connected to negative-phase input terminal, drain terminal being connected to positive-phase output terminal, and gate terminal being supplied with negative-phase local signal.

Abstract: According to an aspect of the invention, an oscillating circuit includes: a first MOS transistor having a first drain terminal and a first source terminal; a load element connected to the first drain terminal; and an oscillator connected to the first source terminal and outputs a fundamental signal and a harmonic signal, wherein the harmonic signal is amplified so that the amplified harmonic signal is output from the first drain terminal.

Abstract: According to one embodiment, a phase-locked loop includes: a voltage controlled oscillator that generates an oscillation signal including an oscillation frequency corresponding to a control signal; a divider that divides the oscillation signal to generate a frequency-divided signal; a phase frequency detector that compares the phases of the frequency-divided signal and a reference signal to generate a comparison signal; a charge pump that outputs current corresponding to the comparison signal; a filter that filters the current to generate the control signal; a detection circuit that generates a detection signal when the difference between a value of a constant multiple of the frequency of the frequency-divided signal and a value of a constant multiple of the frequency of the reference signal becomes local minimum; and a phase adjustment circuit that synchronizes the phases of the frequency-divided signal and the reference signal when the detection signal is generated.

Abstract: A frequency converter includes a first pair of transistors including first and second transistors, a second pair of transistors including third and fourth transistors, and a variable impedance circuit. The first transistor includes source terminal being connected to positive-phase input terminal, drain terminal being connected to positive-phase output terminal, and gate terminal being supplied with positive-phase local signal. The second transistor includes source terminal being connected to positive-phase input terminal, drain terminal being connected to negative-phase output terminal, and gate terminal being supplied with negative-phase local signal. The third transistor includes source terminal being connected to negative-phase input terminal, drain terminal being connected to positive-phase output terminal, and gate terminal being supplied with negative-phase local signal.

Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.

Abstract: According to an aspect of the invention, an oscillating circuit includes: a first MOS transistor having a first drain terminal and a first source terminal; a load element connected to the first drain terminal; and an oscillator connected to the first source terminal and outputs a fundamental signal and a harmonic signal, wherein the harmonic signal is amplified so that the amplified harmonic signal is output from the first drain terminal.

Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.

Abstract: An FMCW signal generator includes a frequency divider to divide the FMCW signal at a preset dividing ratio, a reference signal generator to periodically generate a reference signal at a second time interval not less than a loop time constant set for a PLL, a frequency of the reference signal being discretely swept within a range of fc±?f (fc is a center frequency, and ?f is a frequency sweep width) at a first time interval not more than the loop time constant, a comparison unit to compare the frequency divided signal with the reference signal to generate a comparison result signal corresponding to a phase difference between the frequency divided signal and the reference signal, a loop filter to filter the comparison result signal to generate a control voltage signal, and a VCO to have an oscillation frequency thereof controlled by the control voltage signal.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator to output an oscillation signal of a oscillating frequency in correspondence with a oscillation controlling voltage that is input to the oscillator, a first frequency-divider to subject the oscillation signal to frequency-division and output a first frequency signal, a second frequency-divider to subject the first frequency signal to frequency-division and output a second frequency signal, a controlling voltage generator to generate the oscillation controlling voltage corresponding to a phase difference between a reference clock signal and the second frequency signal, a frequency detector to detect a frequency difference between the second frequency signal and the reference clock signal, and a controller which controls a free-running frequency of the first frequency divider to minimize the frequency difference.

Abstract: Disclosed is a voltage controlled oscillator including: a first element and a second element each passing a current therethrough varying based on a controlled signal; an oscillation circuit configured to generate an oscillation wave in each of a first state in which the current through the first element is current-inputted and a second state in which the current through the second element is current-inputted; a switching circuit switching between the first state and the second state; a current estimation circuit configured to estimate the current through the first element in the first state and to generate an estimation result; and a control circuit configured to generate the control signal for the second element so as to designate a current according to the estimation result as the current through the second element in the second state.

Abstract: A method of manufacturing sugar-added margarine containing 5 to 50% by weight of sugar calculated in terms of its anhydride, characterized in that, an emulsion of oil and fat, and sugar is uniformly heated by means of a micro-wave heating device at a pre-established optimum tempering temperature which is higher than a temperature lower by 10.degree. C. than the increased melting point of the oil and fat with a precision of .+-.2.0.degree. C., and then the heated emulsion is cooled at a rate of not higher than 5.degree. C./hr.