Patents by Inventor Hiroaki IMADE

Hiroaki IMADE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10275015
    Abstract: A power source control executed by a processor includes setting a plurality of period candidates indicating candidates of a predetermined period; calculating, for each of a plurality of nodes, an average interval of idle periods in which a procedure is not executed for each of the plurality of period candidates, based on operation record information indicating history of procedures; calculating an amount of reduction of power consumption with respect to each of the plurality of period candidates based on the calculated average interval and an amount of power consumption in the idle period; selecting a period that is allocated to each of the plurality of nodes from among the plurality of period candidates based on the calculated amount of reduction; and executing, for each of the plurality of nodes, control to set the power source to an off state when the idle period becomes the selected period or more.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Imade, Jun Moroo
  • Publication number: 20180032123
    Abstract: A power source control executed by a processor includes setting a plurality of period candidates indicating candidates of a predetermined period; calculating, for each of a plurality of nodes, an average interval of idle periods in which a procedure is not executed for each of the plurality of period candidates, based on operation record information indicating history of procedures; calculating an amount of reduction of power consumption with respect to each of the plurality of period candidates based on the calculated average interval and an amount of power consumption in the idle period; selecting a period that is allocated to each of the plurality of nodes from among the plurality of period candidates based on the calculated amount of reduction; and executing, for each of the plurality of nodes, control to set the power source to an off state when the idle period becomes the selected period or more.
    Type: Application
    Filed: June 19, 2017
    Publication date: February 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Hiroaki Imade, Jun MOROO
  • Publication number: 20150365343
    Abstract: A plurality of nodes is provided with N-dimensional coordinates identified by N coordinate axes, and a connection relation of the nodes is managed using the N-dimensional coordinates. A management apparatus detects an available free node group from the plurality of nodes, upon acquiring a processing request having specified therein a number of nodes for each coordinate axis for a node group to be used for processing, and converts the number of nodes of two or more coordinate axes out of the number of nodes of the N coordinate axes specified in the processing request, according to the number of nodes aligned in each coordinate axis direction of the free node group. The management apparatus allocates nodes included in the free node group to the processing request, according to the converted number of nodes for each coordinate axis.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 17, 2015
    Inventor: Hiroaki Imade
  • Patent number: 8719821
    Abstract: A process allocation apparatus includes an evaluation value calculating unit, an internode total communication traffic calculating unit, and a correction evaluation value calculating unit. The evaluation value calculating unit calculates an evaluation value of process allocation in accordance with a hop count and inter-process communication traffic from a communication source node to which a process used as a communication source is allocated to a communication destination node to which a process used as a communication destination is allocated. The internode total communication traffic calculating unit specifies a communication route from the communication source node to the communication destination node and calculates internode total communication traffic indicating that the communication traffic between nodes on the specified communication route.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Imade
  • Publication number: 20120304180
    Abstract: A process allocation apparatus includes an evaluation value calculating unit, an internode total communication traffic calculating unit, and a correction evaluation value calculating unit. The evaluation value calculating unit calculates an evaluation value of process allocation in accordance with a hop count and inter-process communication traffic from a communication source node to which a process used as a communication source is allocated to a communication destination node to which a process used as a communication destination is allocated. The internode total communication traffic calculating unit specifies a communication route from the communication source node to the communication destination node and calculates internode total communication traffic indicating that the communication traffic between nodes on the specified communication route.
    Type: Application
    Filed: March 8, 2012
    Publication date: November 29, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Hiroaki IMADE
  • Publication number: 20120303777
    Abstract: A process placement apparatus which places processes in a plurality of nodes which are mutually connected via a network includes a network area divider that divides a network area including the plurality of nodes into a plurality of divided network areas; a process group divider that divides a process group including a plurality of processes into a plurality of divided process groups based on a result of the division of the network area; and a process group placing unit that places each of the plurality of divided process groups in one of the plurality of divided network areas.
    Type: Application
    Filed: March 29, 2012
    Publication date: November 29, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Hiroaki IMADE