Patents by Inventor Hiroaki Ishimura

Hiroaki Ishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9099349
    Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 4, 2015
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoyuki Kofuji, Nobuyuki Negishi, Hiroaki Ishimura
  • Patent number: 9018075
    Abstract: The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 28, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Toru Ito, Hiroaki Ishimura, Akito Kouchi, Hayato Watanabe
  • Publication number: 20140175534
    Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.
    Type: Application
    Filed: August 5, 2013
    Publication date: June 26, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Naoyuki KOFUJI, Nobuyuki NEGISHI, Hiroaki ISHIMURA
  • Publication number: 20140151327
    Abstract: The present invention provides a plasma etching method with an EUV-exposed resist capable of preventing variations of device feature dimensions. The plasma etching method of the present invention is to plasma-etch a target material with a multilayer resist that serves as a mask and composed of an EUV-exposed resist, an antireflective coating, an inorganic film and an organic film. The plasma etching method includes a first step of depositing a deposition film on a surface of the EUV-exposed resist before the antireflective coating is etched, a second step of etching the deposition film deposited on the antireflective coating and the antireflective coating with a gas mixture of Cl2 gas, HBr gas and N2 gas after the first step, a third step of etching the inorganic film after the second step, and a fourth step of etching the organic film after the third step.
    Type: Application
    Filed: February 7, 2013
    Publication date: June 5, 2014
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Satoshi UNE, Hiroaki ISHIMURA, Kouhei MATSUDA
  • Patent number: 8486291
    Abstract: In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takeshi Ohmori, Yasuhiro Nishimori, Hiroaki Ishimura, Hitoshi Kobayashi, Masamichi Sakaguchi
  • Publication number: 20130164911
    Abstract: The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.
    Type: Application
    Filed: February 24, 2012
    Publication date: June 27, 2013
    Inventors: Toru ITO, Hiroaki Ishimura, Akito Kouchi, Hayato Watanabe
  • Patent number: 8207066
    Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: June 26, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yoshiharu Inoue, Hiroaki Ishimura, Hitoshi Kobayashi, Masunori Ishihara, Toru Ito, Toshiaki Nishida
  • Publication number: 20120125890
    Abstract: In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.
    Type: Application
    Filed: January 21, 2011
    Publication date: May 24, 2012
    Inventors: Takeshi OHMORI, Yasuhiro NISHIMORI, Hiroaki ISHIMURA, Hitoshi KOBAYASHI, Masamichi SAKAGUCHI
  • Publication number: 20100255612
    Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.
    Type: Application
    Filed: July 30, 2009
    Publication date: October 7, 2010
    Inventors: Yoshiharu INOUE, Hiroaki ISHIMURA, Hitoshi KOBAYASHI, Masunori ISHIHARA, Toru ITO, Toshiaki NISHIDA
  • Patent number: 7224568
    Abstract: In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: May 29, 2007
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroaki Ishimura, Ken Yoshioka, Takahiro Abe, Go Saito, Motohiko Yoshigai
  • Patent number: 7098138
    Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: August 29, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
  • Publication number: 20060171093
    Abstract: In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.
    Type: Application
    Filed: March 2, 2005
    Publication date: August 3, 2006
    Inventors: Hiroaki Ishimura, Ken Yoshioka, Takahiro Abe, Go Saito, Motohiko Yoshigai
  • Publication number: 20060048892
    Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.
    Type: Application
    Filed: October 20, 2005
    Publication date: March 9, 2006
    Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
  • Publication number: 20040175940
    Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.
    Type: Application
    Filed: April 2, 2003
    Publication date: September 9, 2004
    Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
  • Patent number: 6709984
    Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: March 23, 2004
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
  • Publication number: 20040048477
    Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 11, 2004
    Inventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
  • Publication number: 20040033695
    Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 19, 2004
    Inventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
  • Patent number: 6617255
    Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
  • Publication number: 20010055885
    Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.
    Type: Application
    Filed: March 7, 2001
    Publication date: December 27, 2001
    Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura