Patents by Inventor Hiroaki Ishimura
Hiroaki Ishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9099349Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.Type: GrantFiled: August 5, 2013Date of Patent: August 4, 2015Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Naoyuki Kofuji, Nobuyuki Negishi, Hiroaki Ishimura
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Patent number: 9018075Abstract: The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.Type: GrantFiled: February 24, 2012Date of Patent: April 28, 2015Assignee: Hitachi High-Technologies CorporationInventors: Toru Ito, Hiroaki Ishimura, Akito Kouchi, Hayato Watanabe
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Publication number: 20140175534Abstract: In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.Type: ApplicationFiled: August 5, 2013Publication date: June 26, 2014Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Naoyuki KOFUJI, Nobuyuki NEGISHI, Hiroaki ISHIMURA
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Publication number: 20140151327Abstract: The present invention provides a plasma etching method with an EUV-exposed resist capable of preventing variations of device feature dimensions. The plasma etching method of the present invention is to plasma-etch a target material with a multilayer resist that serves as a mask and composed of an EUV-exposed resist, an antireflective coating, an inorganic film and an organic film. The plasma etching method includes a first step of depositing a deposition film on a surface of the EUV-exposed resist before the antireflective coating is etched, a second step of etching the deposition film deposited on the antireflective coating and the antireflective coating with a gas mixture of Cl2 gas, HBr gas and N2 gas after the first step, a third step of etching the inorganic film after the second step, and a fourth step of etching the organic film after the third step.Type: ApplicationFiled: February 7, 2013Publication date: June 5, 2014Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Satoshi UNE, Hiroaki ISHIMURA, Kouhei MATSUDA
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Patent number: 8486291Abstract: In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.Type: GrantFiled: January 21, 2011Date of Patent: July 16, 2013Assignee: Hitachi High-Technologies CorporationInventors: Takeshi Ohmori, Yasuhiro Nishimori, Hiroaki Ishimura, Hitoshi Kobayashi, Masamichi Sakaguchi
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Publication number: 20130164911Abstract: The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.Type: ApplicationFiled: February 24, 2012Publication date: June 27, 2013Inventors: Toru ITO, Hiroaki Ishimura, Akito Kouchi, Hayato Watanabe
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Patent number: 8207066Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.Type: GrantFiled: July 30, 2009Date of Patent: June 26, 2012Assignee: Hitachi High-Technologies CorporationInventors: Yoshiharu Inoue, Hiroaki Ishimura, Hitoshi Kobayashi, Masunori Ishihara, Toru Ito, Toshiaki Nishida
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Publication number: 20120125890Abstract: In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.Type: ApplicationFiled: January 21, 2011Publication date: May 24, 2012Inventors: Takeshi OHMORI, Yasuhiro NISHIMORI, Hiroaki ISHIMURA, Hitoshi KOBAYASHI, Masamichi SAKAGUCHI
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Publication number: 20100255612Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.Type: ApplicationFiled: July 30, 2009Publication date: October 7, 2010Inventors: Yoshiharu INOUE, Hiroaki ISHIMURA, Hitoshi KOBAYASHI, Masunori ISHIHARA, Toru ITO, Toshiaki NISHIDA
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Patent number: 7224568Abstract: In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.Type: GrantFiled: March 2, 2005Date of Patent: May 29, 2007Assignee: Hitachi High-Technologies CorporationInventors: Hiroaki Ishimura, Ken Yoshioka, Takahiro Abe, Go Saito, Motohiko Yoshigai
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Patent number: 7098138Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.Type: GrantFiled: April 2, 2003Date of Patent: August 29, 2006Assignee: Hitachi, Ltd.Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
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Publication number: 20060171093Abstract: In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.Type: ApplicationFiled: March 2, 2005Publication date: August 3, 2006Inventors: Hiroaki Ishimura, Ken Yoshioka, Takahiro Abe, Go Saito, Motohiko Yoshigai
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Publication number: 20060048892Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.Type: ApplicationFiled: October 20, 2005Publication date: March 9, 2006Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
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Publication number: 20040175940Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.Type: ApplicationFiled: April 2, 2003Publication date: September 9, 2004Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
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Patent number: 6709984Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.Type: GrantFiled: August 13, 2002Date of Patent: March 23, 2004Assignee: Hitachi High-Technologies CorporationInventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
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Publication number: 20040048477Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.Type: ApplicationFiled: September 10, 2003Publication date: March 11, 2004Inventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
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Publication number: 20040033695Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.Type: ApplicationFiled: August 13, 2002Publication date: February 19, 2004Inventors: Go Saito, Hiroaki Ishimura, Yutaka Kudoh, Masamichi Sakaguchi, Kazuo Takata
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Patent number: 6617255Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.Type: GrantFiled: March 7, 2001Date of Patent: September 9, 2003Assignee: Hitachi, Ltd.Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura
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Publication number: 20010055885Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.Type: ApplicationFiled: March 7, 2001Publication date: December 27, 2001Inventors: Takao Arase, Motohiko Yoshigai, Go Saito, Masamichi Sakaguchi, Hiroaki Ishimura, Takahiro Shimomura