Patents by Inventor Hiroaki Iuchi

Hiroaki Iuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140170847
    Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.
    Type: Application
    Filed: January 15, 2013
    Publication date: June 19, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh
  • Publication number: 20140159135
    Abstract: Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Hitomi Fujimoto, Hiroaki Iuchi, Ming Tian, Daisuke Maekawa
  • Publication number: 20130307044
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Inventors: Hiroyuki Kinoshita, Ming Tian, Daisuke Maekawa, Naoki Watakabe, Seiji Shimabukuro, Hiroaki Iuchi, Hitomi Nakajima
  • Patent number: 7759722
    Abstract: When microfabrication is done, a reliable semiconductor device is offered. A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tatsunori Murata, Koyu Asai, Hiroaki Iuchi
  • Publication number: 20080014760
    Abstract: When microfabrication is done, a reliable semiconductor device is offered. A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.
    Type: Application
    Filed: June 20, 2007
    Publication date: January 17, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Tatsunori MURATA, Koyu Asai, Hiroaki Iuchi