Patents by Inventor Hiroaki Katou

Hiroaki Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260198046
    Abstract: A semiconductor device includes a first electrode, a second electrode, a semiconductor part located between the first electrode and the second electrode, a plurality of third electrodes located inside the semiconductor part in at least an element region, a gate electrode positioned between the plurality of third electrodes, and a wiring layer positioned between the semiconductor part and the second electrode. The wiring layer extends from the element region to a termination region. The wiring layer is connected to the plurality of third electrodes in the element region and connected to the second electrode in the termination region.
    Type: Application
    Filed: October 8, 2025
    Publication date: July 9, 2026
    Inventors: Fangyuan Kong, Hiroaki Katou, Toshifumi Nishiguchi
  • Patent number: 12677441
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, first and second conductive parts, first and second gate electrodes, and a first connection part. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The first conductive part is located in the first semiconductor region with a first insulating part interposed. The first gate electrode is located in the first insulating part. The second conductive part is located in the first semiconductor region with a second insulating part interposed. The second gate electrode is located in the second insulating part. The first connection part is located higher than the second and third semiconductor regions. The second electrode is located on the second and third semiconductor regions.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: July 7, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takuya Yasutake, Hiroaki Katou, Hirofumi Kawai, Hiroyuki Kishimoto
  • Patent number: 12666670
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, first to fourth semiconductor regions, a gate electrode, and a second electrode. The third semiconductor region is located on a portion of the second semiconductor region. The fourth semiconductor region includes a first portion positioned on the third semiconductor region and a second portion arranged with the first portion in a second direction. A first-conductivity-type impurity concentration of the first portion is less than a first-conductivity-type impurity concentration of the second portion. The gate electrode faces the second semiconductor region via a gate insulating layer in the second direction. The second electrode is located on the second and fourth semiconductor regions. The second electrode contacts the first and second portions. The second electrode includes a connection part that contacts the third semiconductor region and the portion of the second semiconductor region in the second direction.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: June 23, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Junpei Hisada, Hiroaki Katou
  • Patent number: 12660277
    Abstract: A semiconductor device according to the present embodiment includes: a first electrode; a first semiconductor region of a first conductivity type disposed above the first electrode; a second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region; a second electrode disposed in the first semiconductor region; a third electrode facing the second semiconductor region via a second insulating film; a fourth electrode having a portion adjacent to a part of the second semiconductor region and the third semiconductor region in the second direction, the second semiconductor region, and the third semiconductor region; and a fifth electrode disposed in the first insulating film, having a bottom located closer to the first electrode than a bottom of the portion, having a top located on an upper surface of the first insulating film.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: June 16, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shuhei Tokuyama, Tsuyoshi Kachi, Toshifumi Nishiguchi, Hiroaki Katou
  • Patent number: 12641856
    Abstract: A semiconductor device according to the present embodiment includes a drain electrode, a source electrode, a semiconductor region disposed between the drain electrode and the source electrode, a gate electrode disposed in the semiconductor region via a first insulation film, and a second insulation film disposed between the gate electrode and the source electrode and having a specific dielectric constant higher than a specific dielectric constant of the first insulation film.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 26, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takuya Yasutake, Hiroaki Katou
  • Patent number: 12615828
    Abstract: A semiconductor device includes a first electrode, a second electrode located on the first electrode, a semiconductor part located between the first electrode and the second electrode, a first interconnect located between the semiconductor part and the second electrode, a third electrode located in the semiconductor part and separated from the semiconductor part, a fourth electrode located lower than the third electrode in the semiconductor part, a first plug connecting the second electrode to the fourth electrode, and a second plug. The third electrode includes a ring portion, and an extension portion extending from the ring portion into an interior of the ring portion. The fourth electrode is located in the interior of the ring portion in a plane perpendicular to a vertical direction. The fourth electrode is separated from the semiconductor part. The second plug connects the first interconnect to the extension portion.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: April 28, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Katsura Miyashita, Saya Shimomura, Tsuyoshi Kachi, Tatsuya Nishiwaki
  • Publication number: 20260107502
    Abstract: A semiconductor device includes a first electrode, a second electrode, a semiconductor layer provided between the first electrode and the second electrode in a first direction, a third electrode extending in the first direction within the semiconductor layer and containing silicon, a fourth electrode extending in the first direction within the semiconductor layer, including a first side surface facing a side surface of the third electrode in a second direction orthogonal to the first direction, and a second side surface located on an opposite side of the first side surface in the second direction, an insulating film provided between the second side surface of the fourth electrode and the semiconductor layer and a nitride film in contact with a side surface of the third electrode. The nitride film is located at least in a portion facing a corner between the first side surface and the bottom surface of the fourth electrode on the side surface of the third electrode.
    Type: Application
    Filed: July 28, 2025
    Publication date: April 16, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daichi ISHII, Hiroaki KATOU, Hiroyuki KISHIMOTO
  • Publication number: 20260082626
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor layer, a plurality of third electrodes, a fourth electrode, a first insulating layer, and a wiring part. The semiconductor layer is located between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. The plurality of third electrodes faces the first semiconductor region via a first insulating part. The fourth electrode includes a part positioned between two mutually-adjacent third electrodes. The fourth electrode faces the second semiconductor region via a second insulating part. The first insulating layer is located on the semiconductor layer. The wiring part is located inside the first insulating layer in the cell region. The wiring part extending along the fourth electrode over the fourth electrode. The wiring part is finer than the fourth electrode. The wiring part is electrically connected with the fourth electrode.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 19, 2026
    Inventors: Tsuyoshi KACHI, Hiroaki KATOU
  • Publication number: 20260082624
    Abstract: A semiconductor device according to an embodiment includes a first electrode, a second electrode, and a semiconductor layer. The semiconductor layer includes a first conductivity type first semiconductor region, and a second conductivity type second semiconductor region disposed on the first semiconductor region. The semiconductor device further includes: an insulating region having a cavity extending from an upper end in the first direction; a first control electrode disposed in the insulating region so as to face the second semiconductor region in a second direction ; a second control electrode disposed in the insulating region so as to face the first control electrode in the second direction with the cavity interposed between the first control electrode and the second control electrode; and a conductive portion electrically connected to the first electrode, disposed in the insulating region, and having an upper surface at least partially exposed to a bottom of the cavity.
    Type: Application
    Filed: January 28, 2025
    Publication date: March 19, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazuyuki SATO, Toshifumi Nishiguchi, Tsuyoshi Kachi, Hiroaki Katou
  • Publication number: 20260075911
    Abstract: A semiconductor device includes a substrate including a first surface; a semiconductor layer located on the first surface of the substrate; a plurality of field plate electrodes located inside the semiconductor layer, the plurality of field plate electrodes being positioned at vertices of triangles in a plane parallel to the first surface; and a gate electrode positioned between the plurality of field plate electrodes in the plane parallel to the first surface, a pattern of the gate electrode surrounding a periphery of one of the field plate electrodes being hexagonal, the gate electrode including six side surfaces at the periphery of the one of the field plate electrodes, the semiconductor layer including first side surfaces, the first side surfaces being six equivalent crystal planes respectively facing the six side surfaces of the gate electrode.
    Type: Application
    Filed: January 3, 2025
    Publication date: March 12, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hyuga SAITO, Saya FUJINO, Hiroaki KATOU, Tatsuya NISHIWAKI, Shinya SATO
  • Publication number: 20250386577
    Abstract: A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face and including a first trench provided on a first face side; a first field plate electrode provided in the first trench; a gate electrode provided in a gate trench; a first electrode provided on the first face side of the semiconductor layer and electrically connected to the first field plate electrode; a second electrode provided on the second face side of the semiconductor layer; and a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than an electrical resistance of the first field plate electrode.
    Type: Application
    Filed: November 19, 2024
    Publication date: December 18, 2025
    Inventors: Hiroaki KATOU, Tsuyoshi KACHI, Kazuyuki SATO, Toshifumi NISHIGUCHI
  • Publication number: 20250386542
    Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a semiconductor layer having a first face and a second face; a gate electrode including a second portion and a first portion extending in a first direction in the semiconductor layer; a field plate electrode between the gate electrode and the second face in the semiconductor layer and electrically connected to the first electrode; a conductive layer in the semiconductor layer, provided between the first portion and the second portion, and electrically separated from the first electrode; and a field plate insulating layer between the field plate electrode and the semiconductor layer. A first distance in the first direction between an end of the field plate insulating layer in the first direction on the first face and the conductive layer is smaller than a second distance between the end and the gate electrode in the first direction.
    Type: Application
    Filed: January 24, 2025
    Publication date: December 18, 2025
    Inventors: Toshifumi NISHIGUCHI, Hiroaki KATOU, Tsuyoshi KACHI, Hiroshi HASEGAWA, Shuhei TOKUYAMA
  • Publication number: 20250366023
    Abstract: A semiconductor device includes: a semiconductor portion having a cell region and a terminal region; a first electrode; a second electrode; a control electrode in the semiconductor portion via one of a plurality of first insulators arranged in a direction from the cell region to the terminal region; and a third electrode in the semiconductor portion via a second insulator between itself and the control electrode. The control electrode includes a first controller in contact with the first insulator, and a second controller in contact with the first insulator and opposed to the first controller via the second insulator. Among the plurality of first insulators, an adjacent insulator adjacent to the terminal insulator provided closer to the terminal region than to the control electrode has a slope inclined toward the lower side of the first controller, and the second controller is not present in the slope.
    Type: Application
    Filed: September 13, 2024
    Publication date: November 27, 2025
    Inventors: Hiroaki KATOU, Hirofumi KAWAI, Saya FUJINO, Takuya YASUTAKE, Hyuga SAITO, Atsushi KITO
  • Publication number: 20250366026
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor portion having a cell region and a terminal region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulators arranged in a direction from the cell region to the terminal region; and a third electrode provided in the semiconductor portion via a second insulator between itself and the control electrode. A hollow portion is provided inside a terminal insulator, which is provided closer to the terminal region side than to the control electrode, among the plurality of first insulators.
    Type: Application
    Filed: May 22, 2025
    Publication date: November 27, 2025
    Inventors: Hirofumi KAWAI, Hiroaki KATOU, Saya FUJINO, Takuya YASUTAKE, Hyuga SAITO, Atsushi KITO, Kazuyuki SATO
  • Publication number: 20250329660
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a conductive body, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The conductive body is located in the first semiconductor region with an insulating part interposed. A lower surface of the conductive body includes first and second surfaces. The gate electrode is located in the insulating part. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions.
    Type: Application
    Filed: July 3, 2025
    Publication date: October 23, 2025
    Inventors: Saya SHIMOMURA, Hiroaki KATOU, Yasuhiro KAWAI, Hiroshi YOSHIDA
  • Publication number: 20250318221
    Abstract: A semiconductor device according to the present embodiment includes a semiconductor area, a first electrode, a second electrode, a control electrode, and a third electrode. The semiconductor area includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The semiconductor area further includes a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. A distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in a second region surrounding the first region is smaller than a distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in the first region.
    Type: Application
    Filed: September 9, 2024
    Publication date: October 9, 2025
    Inventors: Hiroaki KATOU, Hirofumi KAWAI, Saya FUJINO, Takuya YASUTAKE, Hyuga SAITO, Atsushi KITO
  • Publication number: 20250318244
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer located on the first electrode, a second semiconductor layer located on the first semiconductor layer, a third semiconductor layer located on the second semiconductor layer, a second electrode facing the second semiconductor layer via an insulating layer, a plurality of contacts, and a third electrode connected to the plurality of contacts. The first semiconductor layer and the third semiconductor layer are of a first conductivity type. The second semiconductor layer is of a second conductivity type. The second semiconductor layer includes a first part and second parts. Distances between the first electrode and the second parts are less than a distance between the first electrode and the first part. The contacts are located respectively in regions directly above the second parts. The contacts are connected to the second and third semiconductor layers.
    Type: Application
    Filed: September 12, 2024
    Publication date: October 9, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki KATOU, Tsuyoshi KACHI
  • Publication number: 20250318223
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor layer; a first and gate electrode extending in a first direction; a second gate electrode extending in the first direction; a first electrode provided on the semiconductor layer; and a second electrode provided on opposites side of the semiconductor layer. The first electrode includes a first portion and a second portion, the first portion and the second portion are provided between the first gate electrode and the second gate electrode, the first portion and the second portion are in contact with the semiconductor layer, the second portion is in the first direction with respect to the first portion, and a second width of the second portion is larger than a first width of the first portion, or a second depth of the second portion is larger than a first depth of the first portion.
    Type: Application
    Filed: September 23, 2024
    Publication date: October 9, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takuya YASUTAKE, Saya FUJINO, Tsuyoshi KACHI, Hiroaki KATOU, Kazuyuki SATO
  • Patent number: 12439675
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, a connecting member, a first member, and an insulating member. The semiconductor member includes first to third semiconductor regions. The first semiconductor region is between the first electrode and the third semiconductor region. The first semiconductor region includes first to third partial regions. The second semiconductor region is between the first and third semiconductor regions. The second semiconductor region includes third and fourth semiconductor portions. The third semiconductor region includes first and second semiconductor portions. The second electrode is electrically connected with the third semiconductor region. The third electrode includes a first electrode portion. The first conductive member includes first to third conductive regions. The connecting member is electrically connected with the first conductive member.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 7, 2025
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shotaro Baba, Hiro Gangi, Hiroaki Katou, Saya Shimomura, Shingo Sato
  • Patent number: 12381155
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a conductive body, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The conductive body is located in the first semiconductor region with an insulating part interposed. A lower surface of the conductive body includes first and second surfaces. The gate electrode is located in the insulating part. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: August 5, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Saya Shimomura, Hiroaki Katou, Yasuhiro Kawai, Hiroshi Yoshida