Patents by Inventor Hiroaki Katsuda

Hiroaki Katsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9660071
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: May 23, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Katou, Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katsuda, Chikako Yoshioka, Yoshitaka Hokomoto
  • Publication number: 20170062604
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion.
    Type: Application
    Filed: March 2, 2016
    Publication date: March 2, 2017
    Inventors: Hiroaki KATOU, Tatsuya NISHIWAKI, Masatoshi ARAI, Hiroaki KATSUDA, Chikako YOSHIOKA, Yoshitaka HOKOMOTO
  • Publication number: 20170040252
    Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.
    Type: Application
    Filed: February 4, 2016
    Publication date: February 9, 2017
    Inventors: Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katou, Hiroaki Katsuda, Chikako Yoshioka, Rieko Matoba
  • Patent number: 9559057
    Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katou, Hiroaki Katsuda, Chikako Yoshioka, Rieko Matoba