Patents by Inventor Hiroaki Kikuchi

Hiroaki Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6583446
    Abstract: An array of light emitting elements, formed as regions of a second conductive type in a semiconductor layer of a first conductive type, includes at least one emission-altering element provided for the purpose of altering the amount of light emitted by an adjacent light-emitting element. The emission-altering element may be a trench, an opaque member, or a non-emitting region of the second conductive type. Light-emitting elements in the interior of the array can be made to emit the same amount of light as the light-emitting elements at the ends of the array by placing one emission-altering element between at least every second pair of mutually adjacent light-emitting elements. If the array is divided into blocks, the emission-altering elements can also provide electrical isolation between the blocks.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: June 24, 2003
    Assignee: Oki Data Corporation
    Inventors: Masumi Taninaka, Hiroaki Kikuchi, Mitsuhiko Ogihara, Hiroshi Hamano
  • Patent number: 6584563
    Abstract: A user support system for cryptographic communication includes a key storage unit for storing keys used for deciphering, a deciphering unit for deciphering an enciphered communication text into a deciphered communication text using a key, and a controller for starting the deciphering unit. only when an input communication text is the enciphered communication text, and for supplying the keys that is necessary for the deciphering in the deciphering unit, by retrieving the key from the key storage.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 24, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Kikuchi, Yasutsugu Kuroda, Hideyuki Aikawa
  • Patent number: 6563321
    Abstract: In a method for detecting a line-short between conductive layers, a potential (or temperature) distribution of the conductive layers is detected while applying a DC voltage thereto. The method is particularly applicable to interdigitated conductive layers. A potential distribution across a wide range perpendicular to the conductors is detected to determine a first location of the line short. Potential distributions between conductors at points parallel to the conductors near the first location are then examined to determine a second location where the potential between the conductors is minimal. Potential distribution at points along a conductor are then examined to determine a location where the potential is sharply changed.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: May 13, 2003
    Assignee: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Publication number: 20030062364
    Abstract: A heating faucet 1 according to the present invention comprises a water supply line 3 connected to a faucet 2 to supply water, and a heating unit 4 mounted in midstream of the water supply line 3 to heat water. The heating unit 4 heats water traveling through the water supply line 3. The heating unit 4 requires only small space when installed, thus enabling effective use of the limited lavatory space within the aircraft. The cost of the heating faucet 1 as a whole is cut down, and the heating unit 4 can be easily mounted to the water supply line 3.
    Type: Application
    Filed: September 18, 2002
    Publication date: April 3, 2003
    Applicant: JAMCO CORPORATION
    Inventors: Hiroaki Kikuchi, Ryoichi Itakura
  • Publication number: 20030034453
    Abstract: A coaxial probe includes a coaxial cable including an electrical conductor extending therethrough and projecting therefrom at an end thereof, a planar waveguide on which the electrical conductor projecting from the coaxial cable is mounted, and a sensor electrically connected to the electrical conductor through the planar waveguide. The planar waveguide may be comprised of a substrate, and a strip line formed on the substrate, the strip line being electrically connected at one end to the sensor and at the other end to the electrical conductor. The sensor may be comprised of a cantilever supported at a distal end thereof on the planar waveguide, and a probe mounted on a free end of the cantilever.
    Type: Application
    Filed: April 20, 2001
    Publication date: February 20, 2003
    Applicant: NEC Corporation
    Inventors: Norio Ookubo, Noriyuki Kodama, Hiroaki Kikuchi, Yuichi Naitou
  • Patent number: 6519373
    Abstract: An image processing apparatus determines whether the longitudinal direction of an image area which is represented by image data inputted in an image processing section and the longitudinal direction of a recording area are correspondent with each other, and then rotates the image by 90 degrees when it is determined that the longitudinal direction of the image area and the longitudinal direction of the recording area are not correspondent with each other.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: February 11, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Hiroaki Kikuchi
  • Patent number: 6495856
    Abstract: A semiconductor random access memory device has stacked capacitor electrodes and test conductive pieces laid on the same pattern as the stacked capacitor electrodes, and the test conductive pieces are alternately isolated from and connected to a ground line, wherein the test conductive pieces are scanned with an electron beam to see whether or not any one of the conductive pieces generates secondary electrons different in intensity from those radiated from the other conductive pieces for detecting a short-circuit, whereby an analyst investigates the stacked capacitor electrodes for a possible short-circuit.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: December 17, 2002
    Assignee: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Patent number: 6496788
    Abstract: When a killer ratio resulting from a specified defect is calculated from die research data including the number of defects and manufacturing result pass/fail for each of a plurality of dies, the die research data is classified based on the number of the specified defects present on a die to calculate a killer ratio for each of a plurality of the classified groups, from which a killer ratio in the case of one specified defect is calculated for each of the groups. The killer ratio for each of the groups is weighted in accordance with the number of the specified defects to calculate one killer ratio as the average value of the weighted killer ratios, thereby calculating one killer ratio which reflects the effect of the number of the specified defects present on a die.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: December 17, 2002
    Assignee: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Patent number: 6445145
    Abstract: A display device capable of removing a defocused beam spot on the focusing screen by obtaining the fluctuation of a focusing voltage following the fluctuation of a high-tension voltage. There is applied a DC voltage of a predetermined high-tension voltage. Also, there is supplied a dynamic focus (DF) correction waveform such as a parabolic waveform voltage or the like matched with horizontal and vertical deflections or the like, for dynamically controlling the focusing in accordance with the shape of the tubular surface of a cathode-ray tube or the like. Further, there is supplied a peak focus (PF) correction waveform voltage corresponding to the fluctuation of the high-tension voltage. The DF correction waveform and the PF correction waveform are added by an adder. An added signal from the adder is amplified by an amplifier to 600 to 800 Vp-p, for example.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: September 3, 2002
    Assignee: Sony Corporation
    Inventors: Satoshi Oosuga, Hiroaki Kikuchi
  • Publication number: 20020051544
    Abstract: A user support system for cryptographic communication includes a key storage for storing keys used for deciphering, a deciphering part for deciphering an enciphered communication text into a deciphered communication text using a key, and a controller for starting the deciphering part only when an input communication text is the enciphered communication text and for supplying the key that is necessary for the deciphering in the deciphering part by retrieving the key from the key storage.
    Type: Application
    Filed: January 2, 2002
    Publication date: May 2, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hiroaki Kikuchi, Yasutsugu Kuroda, Hideyuki Aikawa
  • Patent number: 6346435
    Abstract: An insulating layer is selectively grown on the major surface of a first silicon wafer, and is partially etched away so as to be retracted below the major surface; after the retraction of the insulating layer, the first silicon wafer is bonded to a second silicon wafer, and the major surface of the first silicon wafer is strongly adhered to the major surface of the second silicon wafer, so that the first silicon wafer is hardly separated from the second silicon wafer.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: February 12, 2002
    Assignee: NEC Corporation
    Inventors: Hiroaki Kikuchi, Tomohiro Hamajima
  • Publication number: 20020013665
    Abstract: The present invention provides a method of calculating a kill ratio of an attended defect specie, the method comprising the steps of extracting plural defect specie correspondent sets of die investigation data, and the plural defect specie correspondent sets corresponding to plural recognized defect species, and the plural recognized defect species including not only the attended defect specie but also one or more non-attended defect specie; and implementing a numerical analysis by using the extracted plural defect specie correspondent sets of die investigation data for not only the attended defect specie but also the one or more non-attended defect species, thereby to calculate a kill ratio of the attended defect specie.
    Type: Application
    Filed: June 19, 2001
    Publication date: January 31, 2002
    Applicant: NEC CORPORATION
    Inventor: Hiroaki Kikuchi
  • Publication number: 20010040456
    Abstract: In a method for detecting a line-short between conductive layers, a potential (or temperature) distribution of the conductive layers is detected while applying a DC voltage thereto.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 15, 2001
    Applicant: NEC CORPORATION
    Inventor: Hiroaki Kikuchi
  • Publication number: 20010035525
    Abstract: A semiconductor random access memory device has stacked capacitor electrodes and test conductive pieces laid on the same pattern as the stacked capacitor electrodes, and the test conductive pieces are alternately isolated from and connected to a ground line, wherein the test conductive pieces are scanned with an electron beam to see whether or not any one of the conductive pieces generates secondary electrons different in intensity from those radiated from the other conductive pieces for detecting a short-circuit, whereby an analyst investigates the stacked capacitor electrodes for a possible short-circuit.
    Type: Application
    Filed: April 25, 2001
    Publication date: November 1, 2001
    Applicant: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Patent number: 6310448
    Abstract: Discharge current limiting resistors are provided in respective high-voltage supply lines for distributing high voltages produced by a high-voltage distributor to the anodes of respective CRTs. As a result, a discharge current coming from a high-voltage capacitor that is part of a total discharge current flowing into a CRT where an abnormal discharge has occurred can be reduced to ½ of that in the conventional case and discharge currents coming from coating capacitances of the remaining CRTs that is another part of the total discharge current can be inhibited.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: October 30, 2001
    Assignee: Sony Corporation
    Inventors: Satoshi Oosuga, Hiroaki Kikuchi, Yuusuke Kawamura
  • Patent number: 6274255
    Abstract: A surface material is provided with a first adhesive layer formed by applying a first adhesive composed of a soluble self-digesting adhesive to an adhesive surface and a second adhesive layer formed by applying a second adhesive composed of a two-part synthetic resin contact adhesive to the upper surface of the first adhesive layer. A base material is provided with a base material adhesive layer formed by applying a second adhesive composed of a two-part synthetic resin contact adhesive to an adhesive surface, and having a composition of adhering the second adhesive layer of the surface material and the base material adhesive layer of the base material.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 14, 2001
    Assignee: Jamco Corporation
    Inventors: Hiroaki Kikuchi, Tomio Hayakawa
  • Patent number: 6204075
    Abstract: A circuit, a semiconductor wafer including the circuit and a method for detecting defects of wiring used for detecting a malfunction in a wiring fabrication process during semiconductor device manufacturing. The circuit comprises an insulating film formed on a semiconductor substrate, a first wiring which is formed on the insulating film formed on the semiconductor substrate and is in an electrically floating condition, and a second wiring which is formed on the insulating film formed on the semiconductor substrate and is disposed adjacent to the first wiring and is in an electrically floating condition, wherein the capacitance between the second wiring and the semiconductor substrate is larger than the capacitance between the first wiring and the semiconductor substrate. Portions of the first and second wiring are scanned by an electron beam on the surfaces thereof, and secondary electrons emitted from the first wiring and second wiring are detected.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: March 20, 2001
    Assignee: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Patent number: 6096433
    Abstract: An insulating layer is selectively grown on the major surface of a first silicon wafer, and is partially etched away so as to be retracted below the major surface; after the retraction of the insulating layer, the first silicon wafer is bonded to a second silicon wafer, and the major surface of the first silicon wafer is strongly adhered to the major surface of the second silicon wafer, so that the first silicon wafer is hardly separated from the second silicon wafer.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventors: Hiroaki Kikuchi, Tomohiro Hamajima
  • Patent number: 5999006
    Abstract: A beam of light is projected through an electrolyte to a SOI substrate to scan the surface of the SOI substrate. When the light passes through a pinhole in a buried oxide layer, the light excites a semiconductor layer beneath the buried oxides. An ammeter measures electric charges derived by this light excitation to indicate the presence of pinholes in the buried oxide.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 7, 1999
    Assignee: NEC Corporation
    Inventor: Hiroaki Kikuchi
  • Patent number: 5990964
    Abstract: A method for processing a time code including the steps of generating information, indicating whether or not a location is proper for editing when converting picture information of a predetermined system into picture information of another system, and writing the information to the time code data accompanied with the picture information of the second system.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: November 23, 1999
    Assignees: Sony Corp., Sony Electronics
    Inventors: Tetsuo Ogawa, Hiroshi Kiriyama, Tomokiyo Kato, Hiroaki Kikuchi, Luke Freeman