Patents by Inventor Hiroaki Kitano

Hiroaki Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6085256
    Abstract: A cyber-space system comprising one or more cyber-spaces for providing predetermined information, and user terminals for receiving provision of the predetermined information by accessing the cyber-space, wherein the cyber-space includes information objects for providing information to the user terminals, user objects corresponding to the user terminals, and a conversion object disposed between the information object and the user object, and capable of converting a terminal manipulation message from the user object into an information access message and supplying the converted message to the information object. The conversion object is further capable of converting an information content message from the information object into information corresponding to the capacity of the user terminal and providing the converted information to the user terminal.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: July 4, 2000
    Assignee: Sony Corporation
    Inventors: Hiroaki Kitano, Yasuaki Honda, Akikazu Takeuchi
  • Patent number: 6055536
    Abstract: An information processing system stores information of various types, which is obtained in the real world, in connection with keys indicative of the attribute and feature of the information so that the real-world information is stored quickly and surely in the virtual world which is formed of the linkage of information and stored information of various types is retrieved easily.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: April 25, 2000
    Assignee: Sony Corporation
    Inventors: Masato Shimakawa, Makoto Akabane, Bao Hongchang, Junichi Rekimoto, Hiroaki Kitano, Kazunori Sasano, Kazuo Ishii, Keiichi Yamada, Hiroaki Ogawa, Hiroshi Kakuda, Yasuharu Asano, Hitoshi Honda, Satoshi Fujimura, Atsuo Hiroe
  • Patent number: 5926803
    Abstract: A circuit designing method and apparatus for the design of a large-scale logic circuit. A circuit configuration for a Programmable Logic Device (PLD) is revised in response to a genetic algorithm and then a logic circuit for providing a target output is designed. A collection of grammar rules for feeding out the PLD circuit configuration is applied as a chromosome, and the chromosome (a collection of grammar rules) is revised to feed out the chromosome giving the most suitable circuit configuration. The chromosome length is proportional to the number of grammar rules and does not depend upon the scale of the PLD circuit. Consequently, even for a large PLD circuit, it is possible to design the circuit configuration within a suitable calculating time.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: July 20, 1999
    Assignee: Sony Corporation
    Inventor: Hiroaki Kitano
  • Patent number: 5926116
    Abstract: The invention provides an information retrieval apparatus and an information retrieval method by which information can be retrieved in an improved operability. A CPU controls a video camera to fetch an image and controls a GPS to detect a current position. The CPU reads out, from within image data stored in a corresponding relationship with URLs of WWW servers, those image data which correspond to position data regarding positions around the detected current position from a WWW data base via a modem and a host machine. Then, the CPU selects, from among the read out image data, that image data which matches with the fetched data, reads out a URL corresponding to the image data and accesses a WWW server designated by the URL.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: July 20, 1999
    Assignee: Sony Corporation
    Inventors: Hiroaki Kitano, Junichi Rekimoto
  • Patent number: 5897628
    Abstract: A circuit designing method and apparatus for the design of a large-scale logic circuit. A circuit configuration for a Programmable Logic Device (PLD) is revised in response to a genetic algorithm and then a logic circuit for providing a target output is designed. A collection of grammar rules for feeding out the PLD circuit configuration is applied as a chromosome, and the chromosome (a collection of grammar rules) is revised to feed out the chromosome giving the most suitable circuit configuration. The chromosome length is proportional to the number of grammar rules and does not depend upon the scale of the PLD circuit. Consequently, even for a large PLD circuit, it is possible to design the circuit configuration within a suitable calculating time.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: April 27, 1999
    Assignee: Sony Corporation
    Inventor: Hiroaki Kitano