Patents by Inventor Hiroaki Kouketsu

Hiroaki Kouketsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device having lowered bit line resistance
    Patent number: 9496275
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: November 15, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Hiroaki Kouketsu, Masaya Hosaka
  • SEMICONDUCTOR MEMORY DEVICE HAVING LOWERED BIT LINE RESISTANCE
    Publication number: 20150072497
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: Hiroaki KOUKETSU, Masaya HOSAKA
  • Semiconductor memory device having lowered bit line resistance
    Patent number: 8901637
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 2, 2014
    Assignee: Spansion LLC
    Inventors: Hiroaki Kouketsu, Masaya Hosaka
  • Semiconductor device with reduced transistor breakdown voltage for preventing substrate junction currents
    Patent number: 7626227
    Abstract: A semiconductor device is provided which includes a gate electrode (30) provided on a semiconductor substrate (10), an oxide/nitride/oxide (ONO) film (18) that is formed between the gate electrode (30) and the semiconductor substrate (10) and has a charge storage region (14) under the gate electrode (30), and a bit line (28) that is buried in the semiconductor substrate (10) and includes a low concentration diffusion region (24), a high concentration diffusion region (22) that is formed in the center of the low concentration diffusion region (24) and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line (28) and the semiconductor substrate (10).
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 1, 2009
    Assignee: Spansion LLC
    Inventors: Hiroaki Kouketsu, Masahiko Higashi
  • Semiconductor device and manufacturing method therefor
    Publication number: 20070045720
    Abstract: A semiconductor device is provided which includes a gate electrode (30) provided on a semiconductor substrate (10), an oxide/nitride/oxide (ONO) film (18) that is formed between the gate electrode (30) and the semiconductor substrate (10) and has a charge storage region (14) under the gate electrode (30), and a bit line (28) that is buried in the semiconductor substrate (10) and includes a low concentration diffusion region (24), a high concentration diffusion region (22) that is formed in the center of the low concentration diffusion region (24) and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line (28) and the semiconductor substrate (10).
    Type: Application
    Filed: April 27, 2006
    Publication date: March 1, 2007
    Inventors: Hiroaki Kouketsu, Masahiko Higashi
  • Semiconductor device and fabrication method thereof
    Publication number: 20060244037
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Application
    Filed: January 24, 2006
    Publication date: November 2, 2006
    Inventors: Hiroaki Kouketsu, Masaya Hosaka