Abstract: A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.

Abstract: A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.

Abstract: A D-type flip-flop according to embodiments comprises: a transmission element configured in a slave latch, the transmission element fetching an output of a first latch circuit and outputting the fetched output to a first node, based on a clock signal; a first latch circuit constituting element configured in the first latch circuit, the first latch circuit giving an output of one logical value to the first node through the transmission element with the output fixed in a second mode; and a second latch circuit constituting element configured in the second latch circuit that holds a signal which appears at the first node, the second latch circuit constituting element giving an output of other logical value to the first node based on the clock signal with the output fixed in the second mode.

Abstract: A perpendicular magnetic recording medium according to which both the thermal stability of the magnetization is good and writing with a magnetic head is easy, and moreover the SNR is improved. In the case of a perpendicular magnetic recording medium comprising a nonmagnetic substrate (1), and at least a nonmagnetic underlayer (2), a magnetic recording layer (3), and a protective layer (4) formed in this order on the nonmagnetic substrate (1), the magnetic recording layer (3) comprises a low Ku region (31) layer having a perpendicular magnetic anisotropy constant (Ku value) of not more than 1×105 erg/cm3, and a high Ku region (32) layer having a Ku value of at least 1×106 erg/cm3. Moreover, the magnetic recording layer (3) is made to have therein nonmagnetic grain boundaries that contain a nonmagnetic oxide and magnetically isolate crystal grains, which are made of a ferromagnetic metal, from one another.

Abstract: There is provided a perpendicular magnetic recording medium according to which both the thermal stability of the magnetization is good and writing with a magnetic head is easy, and moreover the SNR is improved. In the case of a perpendicular magnetic recording medium comprising a nonmagnetic substrate 1, and at least a nonmagnetic underlayer 2, a magnetic recording layer 3 and a protective layer 4 formed in this order on the nonmagnetic substrate 1, the magnetic recording layer 3 comprises a low Ku region 31 layer having a perpendicular magnetic anisotropy constant (Ku value) of not more than 1×105 erg/cm3, and a high Ku region 32 layer having a Ku value of at least 1×106 erg/cm3. Moreover, the magnetic recording layer 3 is made to have therein nonmagnetic grain boundaries that contain a nonmagnetic oxide and magnetically isolate crystal grains, which are made of a ferromagnetic metal, from one another.

Abstract: A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data storage circuit configured to store the intermediate calculated value, a changing circuit configured to change data in a following part of the specified byte of the data, a second calculation circuit configured to calculate another error correction code by using the intermediate calculated value and the data in the following part including the changed data, and a data transferring circuit configured to transfer the changed data and the error correction code calculated in the second calculation circuit to the memory.

Abstract: An error detecting and correcting circuit is provided with a syndrome calculating circuit calculating a syndrome of an inputted data sequence including an error correcting code, a polynomial deriving circuit deriving an error location polynomial, a Chien searching circuit obtaining a location of error data of the data sequence, and an error correcting circuit correcting an error of the data, and every time the Chien searching circuit specifies the location of error data, the error correcting circuit immediately corrects the error of the data at the error location, and outputs the corrected data to an external circuit, thereby the error can be efficiently detected and corrected.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data storage circuit configured to store the intermediate calculated value, a changing circuit configured to change data in a following part of the specified byte of the data, a second calculation circuit configured to calculate another error correction code by using the intermediate calculated value and the data in the following part including the changed data, and a data transferring circuit configured to transfer the changed data and the error correction code calculated in the second calculation circuit to the memory.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: There is provided a perpendicular magnetic recording medium according to which both the thermal stability of the magnetization is good and writing with a magnetic head is easy, and moreover the SNR is improved. In the case of a perpendicular magnetic recording medium comprising a nonmagnetic substratel, and at least a nonmagnetic underlayer 2, a magnetic recording layer 3 and a protective layer 4 formed in this order on the nonmagnetic substrate 1, the magnetic recording layer 3 comprises a low Ku region 31 layer having a perpendicular magnetic anisotropy constant (Ku value) of not more than 1×105 erg/cm3, and a high Ku region 32 layer having a Ku value of at least 1×106 erg/cm3. Moreover, the magnetic recording layer 3 is made to have therein nonmagnetic grain boundaries that contain a nonmagnetic oxide and magnetically isolate crystal grains, which are made of a ferromagnetic metal, from one another.

Abstract: The magnetic record/reproduce apparatus for recording and reproducing large amounts of data at ultra-high-speed using a perpendicular magnetic recording mode, comprises: at least a cylinder having a perpendicular magnetic recording layer provided on at least the inner or outer surface thereof; a plurality of magnetic heads arranged to face the perpendicular magnetic recording layer of the cylinder; a rotating means for rotating at least one of the cylinder and the plurality of magnetic heads in relation to the other; a linear driving means for moving at least the cylinder or the plurality of magnetic heads along the axial direction of the cylinder; and a record/reproduce means for recording and/or reproducing data on the perpendicular magnetic recording layer.

Abstract: A thin-film single magnetic pole head which assures highly efficient magnetic energization of a main magnetic pole and which exhibits optimum recording characteristics even in case of recording on a double-layer perpendicular magnetic recording medium with a high frequency. The thin-film single magnetic pole head includes a main magnetic pole consisting of a soft magnetic thin film and a return yoke. A thin-film coil for energizing the main magnetic pole is constituted by a plurality of conductor layers extending substantially parallel to one another and substantially at right angles to the main magnetic pole. The conductor layers are layered together in the up-and-down direction on both sides of the main magnetic pole. A thin-film coil for magnetically energizing the main magnetic pole is constituted by selectively interconnecting the conductors.

Abstract: Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

Abstract: A magnetic thin film head used for perpendicular magnetic recording and reproduction. The head includes a magneto-resistive element and a flux guide made of high permeability thin film whose one end portion faces a perpendicular magnetic recording medium. The magnetic flux produced by the magnetization signal on the perpendicular magnetic recording medium is led to the magneto-resistive element through the flux guide. The head also includes electrodes for supplying an electric current londitudinally to the magneto-resistive element, and high permeability members for introducing the magnetic flux through the magneto-resistive element back to the perpendicular magnetic recording medium. The head further includes a exciting means for the flux guide.