Patents by Inventor Hiroaki Narimatsu

Hiroaki Narimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140193
    Abstract: A capless filler includes a housing, a flap, and a biasing spring. The housing has a fuel hole. The flap includes a supported part, a base, and a protrusion. The supported part is provided at an end part and is supported by the housing. The base extends to the supported part. The protrusion protrudes from the base. The flap is turned on a fulcrum at the supported part between open and closed positions. The biasing spring biases the flap in a direction from the open position to the closed position. The biasing spring pushes the base against an opening rim of the fuel hole at the closed position. The flap is turned in a direction from the closed position to the open position in response to the protrusion being pushed. At least a part of the protrusion is provided as a nozzle guide.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Hiroaki ONUMA, Yukiko NARIMATSU, Hideaki HATAKENAKA, Tsukasa SATO, Kazuyuki SAIKI
  • Patent number: 6756660
    Abstract: A lead frame for a semiconductor device. The lead frame has opposite first and second sides bounded respectively by first and second parallel reference planes between which a thickness is defined. The lead frame has a support with a surface at the first side of the lead frame for receiving a semiconductor chip. A plurality of leads are spaced from the support to be electrically connected to a semiconductor chip on the support. A first lead in the plurality of leads has a length between first and second ends and a width taken transversely to the length. The first end of the first lead has a first region that has a thickness less than the thickness of the first lead at the second end of the first lead so that at least a part of the first region is offset from the second reference plane toward the first reference plane. The first end of the first lead has at least a first protrusion projecting away from the first reference plane.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: June 29, 2004
    Assignee: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi, Hiroaki Narimatsu
  • Publication number: 20030155634
    Abstract: A lead frame for a semiconductor device. The lead frame has opposite first and second sides bounded respectively by first and second parallel reference planes between which a thickness is defined. The lead frame has a support with a surface at the first side of the lead frame for receiving a semiconductor chip. A plurality of leads are spaced from the support to be electrically connected to a semiconductor chip on the support. A first lead in the plurality of leads has a length between first and second ends and a width taken transversely to the length. The first end of the first lead has a first region that has a thickness less than the thickness of the first lead at the second end of the first lead so that at least a part of the first region is offset from the second reference plane toward the first reference plane. The first end of the first lead has at least a first protrusion projecting away from the first reference plane.
    Type: Application
    Filed: December 18, 2002
    Publication date: August 21, 2003
    Applicant: Mitsui High-tec, Inc.
    Inventors: Shoshi Yasunaga, Takahiro Ishibashi, Hiroaki Narimatsu
  • Publication number: 20030096456
    Abstract: A method of manufacturing a semiconductor device. The method includes the steps of: providing a lead frame assembly with joined first and second unit lead frames, with the first unit lead frame having a first support and a plurality of leads and the second unit lead frame having a second support and a plurality of leads; mounting operating components on the first and second unit lead frames; applying a sealing composition over the lead frame assembly and the operating components to define a semiconductor preassembly; cutting the semiconductor preassembly so as to define first and second semiconductor devices, with the first and second semiconductor devices having first and second exposed edges respectively defined by cutting of the semiconductor preassembly; and moving at least the first semiconductor device against another element to break loose flash on the first exposed edge.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 22, 2003
    Applicant: Mitsui High-tec Inc.
    Inventors: Shoshi Yasunaga, Hiroaki Narimatsu, Atsushi Fukui