Abstract: A communication apparatus includes a communication circuit, a clock supply circuit, a CPU and a memory storing a program which, when executed by the CPU, causes the communication apparatus to function as a control unit which causes the communication circuit to operate in one of a first mode in which the communication circuit performs a normal communication with the external apparatus and a second mode in which the communication circuit operates with lower power consumption than in the first mode. In the second mode, the control unit controls the clock supply circuit so as not to supply the clock signal to the communication circuit. While the communication circuit is operating in the second mode and the clock signal is not being supplied to the communication circuit, the control unit controls the clock supply circuit to start supply of the clock signal to the communication circuit in response to a predetermined signal.

Abstract: A communication apparatus includes a communication circuit, a clock supply circuit, a CPU and a memory storing a program which, when executed by the CPU, causes the communication apparatus to function as a control unit which causes the communication circuit to operate in one of a first mode in which the communication circuit performs a normal communication with the external apparatus and a second mode in which the communication circuit operates with lower power consumption than in the first mode. In the second mode, the control unit controls the clock supply circuit so as not to supply the clock signal to the communication circuit. While the communication circuit is operating in the second mode and the clock signal is not being supplied to the communication circuit, the control unit controls the clock supply circuit to start supply of the clock signal to the communication circuit in response to a predetermined signal.

Abstract: An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.

Abstract: An information processing which reduces production costs. The information processing apparatus has a first semiconductor device, a second semiconductor device, a ROM that stores both a first boot program and a second boot program, and an interface for communicating with the ROM. In response to the first semiconductor device being reset, the first semiconductor device reads out the first boot program from the ROM via the interface. In response to the second semiconductor device being reset, the second semiconductor device reads out the second boot program from the ROM via the interface. While the first semiconductor device is reading out the first boot program from the ROM, an output from the second semiconductor device to the interface is controlled to have high impedance.

Abstract: An information processing apparatus includes a first circuit configured to operate by receiving a first voltage or a second voltage higher than the first voltage; a second circuit configured to output a signal indicating which of the first voltage or the second voltage is to be input to the first circuit; and a control unit configured to receive the signal output by the second circuit and to output, to the first circuit, a signal indicating a voltage to be supplied to the first circuit. The control unit is configured to output a signal indicating the second voltage for a period until when the signal output by the second circuit has stabilized, and to output a signal indicating a voltage as indicated by the signal received from the second circuit, after the signal output by the second circuit has stabilized.

Abstract: An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.

Abstract: An image processing method includes determining whether image data acquired by reading a document with a reading unit is color or monochrome, saving color image data determined to be color and monochrome image data generated by monochrome conversion of the color image data, in association with each other as a learning sample, deciding a color conversion parameter to be used when image data read by the reading unit and determined to be monochrome image data is converted into a color image, using the saved learning sample, and converting the image data read by the reading unit and determined to be the monochrome image data into color image data, using the decided color conversion parameter.

Abstract: The image forming apparatus of the present invention includes: a power source unit having a PFC (Power Factor Correction) circuit; a semiconductor integrated circuit including at least one module for performing image processing; and a first power source control unit configured to control whether to turn on or to turn off a power of the PFC circuit, and to control a power control signal input into the semiconductor integrated circuit so that the power of the PFC circuit is on while the power of the module in the semiconductor integrated circuit is on.

Abstract: The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first SRAM configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second SRAM configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first SRAM, continues to supply power to a storage area of the second SRAM in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second SRAM based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied.

Abstract: An image processing method includes determining whether image data acquired by reading a document with a reading unit is color or monochrome, saving color image data determined to be color and monochrome image data generated by monochrome conversion of the color image data, in association with each other as a learning sample, deciding a color conversion parameter to be used when image data read by the reading unit and determined to be monochrome image data is converted into a color image, using the saved learning sample, and converting the image data read by the reading unit and determined to be the monochrome image data into color image data, using the decided color conversion parameter.

Abstract: An image processing apparatus comprises: an obtaining unit configured to obtain image data of an original read by a reading unit; a detection unit configured to detect an object from the image data; a color determination unit configured to determine whether an object detected by the detection unit is a color image or a monochrome image; a conversion unit configured to convert each object determined to be a monochrome image by the color determination unit into a color image; and a display unit configured to perform a display, for each object converted by the conversion unit, in which editing by a user is possible.

Abstract: The image forming apparatus of the present invention includes: a power source unit having a PFC (Power Factor Correction) circuit; a semiconductor integrated circuit including at least one module for performing image processing; and a first power source control unit configured to control whether to turn on or to turn off a power of the PFC circuit, and to control a power control signal input into the semiconductor integrated circuit so that the power of the PFC circuit is on while the power of the module in the semiconductor integrated circuit is on.

Abstract: An information processing apparatus includes a first circuit configured to operate by receiving a first voltage or a second voltage higher than the first voltage; a second circuit configured to output a signal indicating which of the first voltage or the second voltage is to be input to the first circuit; and a control unit configured to receive the signal output by the second circuit and to output, to the first circuit, a signal indicating a voltage to be supplied to the first circuit. The control unit is configured to output a signal indicating the second voltage for a period until when the signal output by the second circuit has stabilized, and to output a signal indicating a voltage as indicated by the signal received from the second circuit, after the signal output by the second circuit has stabilized.

Abstract: The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first SRAM configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second SRAM configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first SRAM, continues to supply power to a storage area of the second SRAM in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second SRAM based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied.

Abstract: The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first SRAM configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second SRAM configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first SRAM, continues to supply power to a storage area of the second SRAM in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second SRAM based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied.

Abstract: An information processing which reduces production costs. The information processing apparatus has a first semiconductor device, a second semiconductor device, a ROM that stores both a first boot program and a second boot program, and an interface for communicating with the ROM. In response to the first semiconductor device being reset, the first semiconductor device reads out the first boot program from the ROM via the interface. In response to the second semiconductor device being reset, the second semiconductor device reads out the second boot program from the ROM via the interface. While the first semiconductor device is reading out the first boot program from the ROM, an output from the second semiconductor device to the interface is controlled to have high impedance.

Abstract: The image forming apparatus of the present invention is a semiconductor integrated circuit including: a first image processing module; a second image processing module; a first SRAM configured to temporarily store image data for which the first image processing has been performed by the first image processing module; a second SRAM configured to store a parameter for performing the second image processing for image data that is input to the second image processing module; and a control unit. The control unit stops power supply to the first SRAM, continues to supply power to a storage area of the second SRAM in which the parameter is stored, and stops power supply to a control area for writing data to the storage area of the second SRAM based on that a condition to cause the semiconductor integrated circuit to make a transition into a power-saving mode is satisfied.

Abstract: An information processing apparatus that improves the convenience of a user who performs authentication using an authentication medium. A communication system module acquires authentication information from an IC card. A sensor system module detects proximity of the IC card. A main circuit element group authenticates a user using the acquired authentication information. A power supply controller supplies power to those modules and the group. A power supply destination is controlled such that the apparatus is shifted to a power saving state in which power is supplied only to the sensor system module. In the power saving state, when the sensor system module detects proximity of the IC card, the power supply destination is controlled to cause the apparatus to shift to a normal power state in which power is supplied to the communication system module and the main circuit element group.

Abstract: A semiconductor integrated circuit includes, a fixed frequency-division clock generation unit configured to generate a fixed frequency-division clock with a fixed frequency based on an output clock of a clock source, a variable frequency-division clock generation unit configured to generate a variable frequency-division clock with a variable frequency based on the output clock of the clock source, and a data path selection unit configured to select a data path. The data path selection unit selects a data path with or without a synchronization unit for converting the data into clock-synchronous data on a receiving side according to whether the variable frequency-division clock is or is not, respectively, generated by the variable frequency-division clock generation unit.

Abstract: A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed.