Abstract: An anonymization system is equipped with a provisioning data manager, a provisioning rule manager, and an issuer. Upon receiving data that contains predetermined information and provisioning rules that correspond to the data and are used as conditions under which the data is anonymized, the provisioning data manager stores the data and provides the provisioning rules. The provisioning rule manager stores the provisioning rules provided by the provisioning data manager. When a request is made to issue the anonymized data, that is, the data that has been anonymized, if the issuance request is in accord with the provisioning rules stored in the provisioning rule manager, the issuer acquires the data corresponding to the provisioning rules from the provisioning data manager, issues the anonymized data by anonymizing the acquired data, and provides the anonymized data.

Abstract: An anonymization system is equipped with a provisioning data manager, a provisioning rule manager, and an issuer. Upon receiving data that contains predetermined information and provisioning rules that correspond to the data and are used as conditions under which the data is anonymized, the provisioning data manager stores the data and provides the provisioning rules. The provisioning rule manager stores the provisioning rules provided by the provisioning data manager. When a request is made to issue the anonymized data, that is, the data that has been anonymized, if the issuance request is in accord with the provisioning rules stored in the provisioning rule manager, the issuer acquires the data corresponding to the provisioning rules from the provisioning data manager, issues the anonymized data by anonymizing the acquired data, and provides the anonymized data.

Abstract: Design apparatuses according to the present embodiments each include a CDFG generator, a scheduler, a binder, a retention register selector, a control circuit generator, and an RTL description generator. The binder generates a data path circuit in which a hardware element is allocated to a CDFG after scheduling by the scheduler. The retention register selector detects, as a retention control step, one of the control steps which has a minimum number of latch bits from the CDFG after scheduling and selects, as a retention register, a register allocated to the detected retention control step. The control circuit generator generates a control circuit which performs an execution control of the data path circuit and causes a state to transition to the retention control step when a signal for power-off is enabled.

Abstract: A behavioral synthesis apparatus includes a control data flow graph generator that generates a CDFG specifying an execution order of calculations written in a behavior description including an external loop processing that includes internal loops processing which does not expand the internal loops processing, a scheduling module carries out scheduling of calculations, and an assigning module divides first pipeline processing for implementing the external loop processing and second pipeline processing for implementing the internal loops processing into stages, and assigns pipeline registers to the external loop processing and the internal loops processing.

Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Abstract: A behavioral synthesis apparatus includes a control data flow graph generator that generates a CDFG specifying an execution order of calculations written in a behavior description including an external loop processing that includes internal loops processing which does not expand the internal loops processing, a scheduling module carries out scheduling of calculations, and an assigning module divides first pipeline processing for implementing the external loop processing and second pipeline processing for implementing the internal loops processing into stages, and assigns pipeline registers to the external loop processing and the internal loops processing.

Abstract: In a high-speed serial-to-parallel conversion transmission system, a transmitter inserts pattern data composed of a combination of a plurality of idle characters in a signal to be transmitted such that a receiver measures an amount of skew, while the receiver measures the amount of skew and performs delay control over the received signal. By using the idle characters as the pattern data, a skew compensation pattern can be inserted as invalid data in a transmitted data stream containing valid data.

Abstract: An instruction generator comprising a storage device configured to store a machine instruction function incorporating both an operation definition defining a program description in a source program targeted for substitution to a SIMD instruction, and the SIMD instruction. A parallelism analyzer is configured to analyze the source program so as to detect operators applicable to parallel execution, and to generate parallelism information indicating the set of operators applicable to parallel execution. A SIMD instruction generator is configured to perform a matching determination between an instruction generating rule for the SIMD instruction and the parallelism information, and to read the machine instruction function out of the storage device in accordance with a result of the matching determination.

Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Abstract: In a high-speed serial-to-parallel conversion transmission system, a transmitter inserts pattern data composed of a combination of a plurality of idle characters in a signal to be transmitted such that a receiver measures an amount of skew, while the receiver measures the amount of skew and performs delay control over the received signal. By using the idle characters as the pattern data, a skew compensation pattern can be inserted as invalid data in a transmitted data stream containing valid data.

Abstract: Disclosed is a proposal for a technique of classifying communication for Layers 1 and 2 or higher, and thereby establishment of a necessary method of safely and simply interchanging a secret key, an authentication method, an error detection method, and a recovery method. It is necessary to decrease the amount of hardware needed for establishing these. We invented a hardware-based method of safely and simply interchanging a key needed for classified connection. A procedure according to the invention interchanges a key using a feature attributed to a classification conversion to which an commutative law is applicable. The procedure can simultaneously confirm normal connection of both outward and homeward routes and is also usable as an DC balanced encoding system as a result of classification. Layers 1 and 2 can be classified because the classified connection is based on hardware.

Abstract: A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

Abstract: A model of architecture of a processor is called an architecture template. Because a designer selects an architecture template of a special purpose processor which is suitable for an objective signal processing algorithm from an architecture template library, a special purpose processor which is the most suitable for any signal algorithm can be synthesized. Moreover, by providing a method of creating an architecture template simply, even if there is no desirable architecture template, an objective architecture template can be synthesized for a short time.

Abstract: Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them.

Abstract: Disclosed is an integrated semiconductor circuit device which has a plurality of cell arrays formed in parallel on a surface region of the substrate, and a three-layer wire formed on the substrate and between each cell array. The direction of a wire track of a second layer wire is originally determined in a direction parallel to the cell arrays, and the direction of wire tracks of first and third layer wires is originally determined in a direction orthogonal to the originally determined direction of the wire track of the second layer wire. The first layer wire and the third layer wire are formed on the same wire track. Part of the third layer wire is formed on a wire track orthogonal to the originally determined direction of the wire track of the third layer, and the third layer wire and the second layer wire are connected to each other on the wire track which is orthogonal to the originally determined direction of the wire track of the third layer wire.

Abstract: A method for treating a sugar solution in which one, two or more than two kinds of esters selected from the group consisting of glycerol mono-aceto mono-fatty acid ester, glycerol mono-aceto di-fatty acid ester and glycerol di-aceto mono-fatty acid ester composed of a fatty acid of 12 carbons or composed of mixed fatty acids consisting at least 40% of a fatty acid of 12 carbons and the rest being fatty acids of 8 to 14 carbons are added to the sugar solution during a process of manufacturing sugars.