Patents by Inventor HIROAKI NISHIYA

HIROAKI NISHIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240378877
    Abstract: A memory region is suppressed. An imaging device according to the present disclosure includes: a sensor that outputs first image data; a first processing unit that executes processing of a first layer in a neural network having a layered structure on the first image data in units of second image data having a size smaller than an entire size of the first image data; and a second processing unit that executes processing of a second layer in the neural network on a processing result output from the first processing unit.
    Type: Application
    Filed: June 3, 2022
    Publication date: November 14, 2024
    Applicant: Sony Semiconductor Solutions Corporation
    Inventor: Hiroaki NISHIYA
  • Patent number: 11252357
    Abstract: The present technology relates to an image-capturing device and an electronic apparatus that are capable of reducing kTC noise. A sample-hold unit that performs sampling and holding of a pixel signal, an analog-digital (AD) conversion unit that performs AD conversion of the pixel signal, and a setting unit that sets a transconductance of an operational amplifier included in the sample-hold unit to a transconductance where kTC noise is minimized are included. Alternatively, a sample-hold unit that performs sampling and holding of a pixel signal, a kTC cancellation unit that reduces kTC noise in the sample-hold unit, an analog-digital (AD) conversion unit that performs AD conversion of the pixel signal, and a setting unit that sets a capacitance value of a capacitor included in the kTC cancellation unit to a capacitance value where the kTC noise is minimized are included.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: February 15, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Chihiro Okada, Hiroaki Nishiya
  • Publication number: 20200412987
    Abstract: The present technology relates to an image-capturing device and an electronic apparatus that are capable of reducing kTC noise. A sample-hold unit that performs sampling and holding of a pixel signal, an analog-digital (AD) conversion unit that performs AD conversion of the pixel signal, and a setting unit that sets a transconductance of an operational amplifier included in the sample-hold unit to a transconductance where kTC noise is minimized are included. Alternatively, a sample-hold unit that performs sampling and holding of a pixel signal, a kTC cancellation unit that reduces kTC noise in the sample-hold unit, an analog-digital (AD) conversion unit that performs AD conversion of the pixel signal, and a setting unit that sets a capacitance value of a capacitor included in the kTC cancellation unit to a capacitance value where the kTC noise is minimized are included. The present technology can be applied to a CMOS image sensor, for example.
    Type: Application
    Filed: February 20, 2019
    Publication date: December 31, 2020
    Inventors: CHIHIRO OKADA, HIROAKI NISHIYA