Patents by Inventor Hiroaki Shimauchi

Hiroaki Shimauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8265087
    Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 11, 2012
    Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Patent number: 8122316
    Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: February 21, 2012
    Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Patent number: 8041747
    Abstract: A data search device that is provided in a communication apparatus detects a memory area storing data to be transmitted from a memory unit having memory areas defined by IDs allotted to data. The data search device includes: a first flag that is provided for each of the memory areas of the memory unit, and indicate whether the data in the corresponding memory area is updated; a second flag that is provided for each group consisting of a predetermined number of the first flags, and indicates a data update state when at least one set of data in the first flags in the corresponding group indicates an updated state; and a search control unit that detects the memory area storing the data to be transmitted, by searching for the corresponding first flag after detecting the second flag.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: October 18, 2011
    Assignees: Fujitsu Ten Limited, Toyota Jidosha Kabushiki Kaisha
    Inventors: Susumu Nishihashi, Shinji Yamashita, Kenji Hontani, Yukio Fujisawa, Satoshi Yamanaka, Hiroaki Shimauchi
  • Patent number: 8027352
    Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: September 27, 2011
    Assignees: Fujitsu Semiconductor Limited, Renesas Technology Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Publication number: 20090210397
    Abstract: A data search device that is provided in a communication apparatus detects a memory area storing data to be transmitted from a memory unit having memory areas defined by IDs allotted to data. The data search device includes: a first flag that is provided for each of the memory areas of the memory unit, and indicate whether the data in the corresponding memory area is updated; a second flag that is provided for each group consisting of a predetermined number of the first flags, and indicates a data update state when at least one set of data in the first flags in the corresponding group indicates an updated state; and a search control unit that detects the memory area storing the data to be transmitted, by searching for the corresponding first flag after detecting the second flag.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 20, 2009
    Applicants: FUJITSU TEN LIMITED, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Susumu Nishihashi, Shinji Yamashita, Kenji Hontani, Yukio Fujisawa, Satoshi Yamanaka, Hiroaki Shimauchi
  • Publication number: 20080141074
    Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
    Type: Application
    Filed: October 25, 2007
    Publication date: June 12, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Publication number: 20080101394
    Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 1, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORPORATION
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Publication number: 20080101393
    Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 1, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Patent number: 5836775
    Abstract: A connector apparatus for a card-like data processing medium comprises a frame (12) having opposing side walls (16a, 16b) that define a storage space (24a, 24b) of the connector apparatus. One end of the frame (12) defines an insertion inlet (22) for inserting a card-like data processing medium (30) in the storage space. A header containing a terminal array (32) is coupled to the end of the frame opposite the insertion inlet (22). An ejection mechanism (40a, 40b) is provided for ejecting the card-like data processing medium (30) from the storage space by manual operation of a push rod (48) that is coupled to the ejection mechanism (40). Means responsive to a control signal are provided for automatically decoupling the push rod (48) from the ejection mechanism to desable the ejection mechanism.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: November 17, 1998
    Assignee: Berg Tehnology, Inc.
    Inventors: Naoki Hiyama, Kenji Suzuki, Vincent D. Dimondi, Nobuei Takai, Nai Hock Lwee, Hiroshi Masuda, Hiroaki Shimauchi