Patents by Inventor Hiroaki Shishido

Hiroaki Shishido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7791725
    Abstract: An inspection apparatus and method includes a light source which emits an ultraviolet laser beam, an illuminating unit having a polarization controller and an object lens for illuminating a specimen with light emitted from the light source and passed through the polarization controller and the object lens, a detection unit having a sensor for detecting light from the specimen illuminated by the illuminating unit, a processor which processes a signal output from the sensor so as to detect a defect on the specimen, and a display which displays information output from the processor. The processor processes an image formed from the signal output from the sensor in which the image is reduced in speckle pattern.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: September 7, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Patent number: 7573109
    Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: August 11, 2009
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
  • Publication number: 20090073443
    Abstract: An inspection apparatus and method includes a light source which emits an ultraviolet laser beam, an illuminating unit having a polarization controller and an object lens for illuminating a specimen with light emitted from the light source and passed through the polarization controller and the object lens, a detection unit having a sensor for detecting light from the specimen illuminated by the illuminating unit, a processor which processes a signal output from the sensor so as to detect a defect on the specimen, and a display which displays information output from the processor. The processor processes an image formed from the signal output from the sensor in which the image is reduced in speckle pattern.
    Type: Application
    Filed: November 14, 2008
    Publication date: March 19, 2009
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Patent number: 7456963
    Abstract: An Inspection apparatus and method includes utilizing an emitter which emits a light beam, an illumination optical system, a detection optical system, and a processor. The illumination optical system includes a polarization controller, a coherence reducer, and an objective lens, for illuminating a specimen with a polarization condition controlled and coherency reduced light beam through the objective lens. The detection optical system includes an imaging lens and a sensor for detecting an image of the specimen illuminated by the light beam through the illumination optical system. The processor processes a signal outputted from the sensor and detects a defect on the specimen.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 25, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Patent number: 7365391
    Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 29, 2008
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
  • Patent number: 7282764
    Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: October 16, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
  • Patent number: 7251024
    Abstract: A defect inspection apparatus for inspecting a fine circuit pattern with high resolution to detect a defective portion is constructed to have an objective lens for detecting an image of a sample, a laser illumination unit for illuminating the sample through the objective lens, a unit for reducing the coherence of the laser illumination, an accumulation type detector, and a unit for processing the detected image signal.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: July 31, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Shunji Maeda, Atsushi Yoshida, Yukihiro Shibata, Minoru Yoshida, Sachio Uto, Hiroaki Shishido, Toshihiko Nakata
  • Patent number: 7208375
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: April 24, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20070069323
    Abstract: A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90<Q2/Q1 when Wm1<WPE<Wm2.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 29, 2007
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
  • Patent number: 7196376
    Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 27, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.,
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
  • Publication number: 20070052955
    Abstract: An Inspection apparatus and method includes utilizing an emitter which emits a light beam, an illumination optical system, a detection optical system, and a processor. The illumination optical system includes a polarization controller, a coherence reducer, and an objective lens, for illuminating a specimen with a polarization condition controlled and coherency reduced light beam through the objective lens. The detection optical system includes an imaging lens and a sensor for detecting an image of the specimen illuminated by the light beam through the illumination optical system. The processor processes a signal outputted from the sensor and detects a defect on the specimen.
    Type: Application
    Filed: November 6, 2006
    Publication date: March 8, 2007
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Publication number: 20070045726
    Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 1, 2007
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
  • Publication number: 20070045776
    Abstract: A semiconductor device having high ruggedness is provided. The distance Wm2 between buried regions, positioned at the bottoms of different base diffusion regions and face each other, is set smaller than the distance Wm1 between buried regions positioned at the bottom of the same base diffusion region (Wm1>Wm2). An avalanche breakdown occurs under the bottom of the base diffusion region, and the avalanche current is not passed through a high resistance part immediately under the source diffusion region in the base diffusion region, thereby providing high withstand strength against destruction.
    Type: Application
    Filed: July 6, 2006
    Publication date: March 1, 2007
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shinji Kunori, Hiroaki Shishido, Masato Mikawa, Kosuke Ohshima, Masahiro Kuriyama, Mizue Kitada
  • Patent number: 7132669
    Abstract: An Inspection apparatus and method includes utilizing a laser source which emits an ultraviolet laser beam, an illumination optical system, a detection optical system, and a processor. The illumination optical system includes a polarization controller, a coherence reducer and an objective lens for illuminating a specimen with a polarization condition controlled and coherency reduced ultraviolet laser beam through the objective lens. The detection optical system includes an imaging lens and a sensor for detecting an image of the specimen illuminated by the ultraviolet laser beam through the illumination optical system. The processor processes a signal outputted from the sensor and detects a defect on the specimen.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: November 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Publication number: 20060063335
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Application
    Filed: October 19, 2004
    Publication date: March 23, 2006
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20050253081
    Abstract: An Inspection apparatus and method includes utilizing a laser source which emits an ultraviolet laser beam, an illumination optical system, a detection optical system, and a processor. The illumination optical system includes a polarization controller, a coherence reducer and an objective lens for illuminating a specimen with a polarization condition controlled and coherency reduced ultraviolet laser beam through the objective lens. The detection optical system includes an imaging lens and a sensor for detecting an image of the specimen illuminated by the ultraviolet laser beam through the illumination optical system. The processor processes a signal outputted from the sensor and detects a defect on the specimen.
    Type: Application
    Filed: July 20, 2005
    Publication date: November 17, 2005
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Publication number: 20050224848
    Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 13, 2005
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
  • Patent number: 6921905
    Abstract: Inspection apparatus and method in which laser source emits a laser beam and a coherence of the laser beam emitted from the laser source is reduced by a coherence reducer. A detector detects light from the sample irradiated with the coherence reduced laser beam and a processor processes a signal outputted from the detector and detects a defect on the sample. The coherence reducer has an optical path which includes a plurality of at least one of optical fibers and glass rods.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: July 26, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Shishido, Yasuhiro Yoshitake, Toshihiko Nakata, Shunji Maeda, Minoru Yoshida, Sachio Uto
  • Patent number: 6906355
    Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: June 14, 2005
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20050083519
    Abstract: A defect inspection apparatus for inspecting a fine circuit pattern with high resolution to detect a defective portion is constructed to have an objective lens for detecting an image of a sample, a laser illumination unit for illuminating the sample through the objective lens, a unit for reducing the coherence of the laser illumination, an accumulation type detector, and a unit for processing the detected image signal.
    Type: Application
    Filed: October 25, 2004
    Publication date: April 21, 2005
    Inventors: Shunji Maeda, Atsushi Yoshida, Yukihiro Shibata, Minoru Yoshida, Sachio Uto, Hiroaki Shishido, Toshihiko Nakata