Patents by Inventor Hiroaki Taketani
Hiroaki Taketani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11706909Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: October 28, 2020Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Patent number: 11217588Abstract: Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: July 3, 2019Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Mitsunari Sukekawa, Hiroaki Taketani
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Patent number: 11139302Abstract: Some embodiments include an integrated assembly having bitlines spaced from one another by intervening voids. Insulative supports are over the bitlines. A conductive plate is supported by the insulative supports and is proximate the bitlines to drain excess charge from the bitlines. Some embodiments include a method of forming an integrated assembly. A stack is formed to have insulative material over bitline material. The stack is patterned into rails that extend along a first direction. The rails include the patterned bitline material as bitlines, and include the patterned insulative material as insulative supports over the bitlines. The rails are spaced from one another along a second direction, orthogonal to the first direction, by voids. Sacrificial material is formed within the voids. A conductive plate is formed over the insulative supports and the sacrificial material. The sacrificial material is removed from under the conductive plate to re-form the voids.Type: GrantFiled: June 10, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Mitsunari Sukekawa, Hiroaki Taketani
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Publication number: 20210074705Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 28, 2020Publication date: March 11, 2021Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Patent number: 10910379Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 15, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Patent number: 10896909Abstract: Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: June 13, 2019Date of Patent: January 19, 2021Assignee: Micron Technology, Inc.Inventors: Shingo Ujihara, Hiroaki Taketani
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Publication number: 20210005611Abstract: Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Applicant: Micron Technology, Inc.Inventors: Mitsunari Sukekawa, Hiroaki Taketani
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Publication number: 20200388619Abstract: Some embodiments include an integrated assembly having bitlines spaced from one another by intervening voids. Insulative supports are over the bitlines. A conductive plate is supported by the insulative supports and is proximate the bitlines to drain excess charge from the bitlines. Some embodiments include a method of forming an integrated assembly. A stack is formed to have insulative material over bitline material. The stack is patterned into rails that extend along a first direction. The rails include the patterned bitline material as bitlines, and include the patterned insulative material as insulative supports over the bitlines. The rails are spaced from one another along a second direction, orthogonal to the first direction, by voids. Sacrificial material is formed within the voids. A conductive plate is formed over the insulative supports and the sacrificial material. The sacrificial material is removed from under the conductive plate to re-form the voids.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Applicant: Micron Technology, Inc.Inventors: Mitsunari Sukekawa, Hiroaki Taketani
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Publication number: 20200295008Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Micron Technology, Inc.Inventors: Sanh D. Tang, Mitsunari Sukekawa, Yusuke Yamamoto, Christopher J. Kawamura, Hiroaki Taketani
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Publication number: 20190326297Abstract: Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: June 13, 2019Publication date: October 24, 2019Applicant: Micron Technology, Inc.Inventors: Shingo Ujihara, Hiroaki Taketani
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Patent number: 10347639Abstract: Some embodiments include an integrated assembly having a first semiconductor material configured to comprise a pair of pedestals. The pedestals have upper regions which are separated from one another by a space, and have lower regions which join to one another at a floor region beneath the space. A second semiconductor material is configured as a bridge extending between the pedestals. The bridge is spaced from the floor region by a gap. The bridge has ends adjacent the pedestals, and has a body region between the ends. The body region has an outer periphery. Source/drain regions are within the pedestals, and a channel region is within the bridge. A dielectric material extends around the outer periphery of the body region of the bridge. A conductive material extends around the dielectric material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 19, 2018Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: Shingo Ujihara, Hiroaki Taketani
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Patent number: 9496383Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.Type: GrantFiled: June 18, 2014Date of Patent: November 15, 2016Assignee: Longitude Semiconductor S.a.r.l.Inventors: Kiyonori Oyu, Koji Taniguchi, Koji Hamada, Hiroaki Taketani
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Patent number: 9305926Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: GrantFiled: February 23, 2015Date of Patent: April 5, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Hiroaki Taketani
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Publication number: 20150171089Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: ApplicationFiled: February 23, 2015Publication date: June 18, 2015Inventor: Hiroaki TAKETANI
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Patent number: 9041085Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.Type: GrantFiled: April 27, 2012Date of Patent: May 26, 2015Assignee: PS4 LUXCO S.A.R.L.Inventors: Kiyonori Oyu, Koji Taniguchi, Koji Hamada, Hiroaki Taketani
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Patent number: 8987799Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: GrantFiled: August 7, 2014Date of Patent: March 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Hiroaki Taketani
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Publication number: 20140346595Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventor: Hiroaki TAKETANI
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Publication number: 20140299928Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure.Type: ApplicationFiled: June 18, 2014Publication date: October 9, 2014Inventors: Kiyonori OYU, Koji TANIGUCHI, Koji HAMADA, Hiroaki TAKETANI
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Patent number: 8829583Abstract: A semiconductor device includes a semiconductor device may include, but is not limited to, a semiconductor substrate, an isolation electrode, a gate electrode, a gate insulating film, and a first insulating film. The semiconductor substrate has a first groove and a second groove. An isolation electrode is positioned in the first groove. The gate electrode is positioned in the second groove. The gate insulating film is adjacent to the gate electrode. The first insulating film is adjacent to the isolation electrode. The isolation electrode is greater in threshold voltage than the gate electrode.Type: GrantFiled: February 15, 2012Date of Patent: September 9, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Hiroaki Taketani
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Patent number: 8373226Abstract: In Trench-Gate Fin-FET, in order that the advantage which is exerted in Fin-FET can be sufficiently taken even if a transistor becomes finer and, at the same time, decreasing of on-current can be suppressed by saving a sufficiently large contact area in the active region, a fin width 162 of a channel region becomes smaller than a width 161 of an active region.Type: GrantFiled: August 26, 2010Date of Patent: February 12, 2013Assignee: Elpida Memory, Inc.Inventor: Hiroaki Taketani