Patents by Inventor Hiroaki Takikawa

Hiroaki Takikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9390941
    Abstract: There is provided a VUV light processing apparatus that can apply vacuum ultraviolet light to the entire surface of a wafer in excellent reproducibility and can process the wafer with VUV (vacuum ultraviolet) light in excellent reproducibility. A VUV light processing apparatus includes: a chamber connected with a gas supply apparatus and an evacuation apparatus, the chamber being capable of reducing the pressure inside the chamber; a plasma light source that generates VUV light including a wavelength of 200 nm or less, the plasma light source including a plasma generating unit that generates plasma in the chamber; and a VUV transmission filter provided between a stage on which a sample to be processed is placed and the sample in the chamber, the VUV transmission filter transmitting the VUV light including a wavelength of 200 nm or less and not transmitting electrons, ions, and radicals in plasma, the VUV transmission filter having the outer diameter size larger than that of the sample.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: July 12, 2016
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Seiichi Watanabe, Yutaka Kozuma, Tooru Aramaki, Naoki Yasui, Norihiko Ikeda, Hiroaki Takikawa
  • Publication number: 20150114568
    Abstract: A plasma processing apparatus including a wafer stage disposed in a processing chamber arranged in a vacuum chamber to hold a wafer as a processing object on a surface of the wafer stage, to conduct processing for the wafer by use of plasma, wherein the wafer includes grooves, each of the grooves extending from a central portion of a surface on which the wafer is held to an outer circumferential edge of the surface, the grooves including openings at the outer circumferential edge, and the processing is conducted in a state in which the wafer is held at predetermined height over an upper surface of the wafer stage.
    Type: Application
    Filed: February 17, 2014
    Publication date: April 30, 2015
    Inventors: Yutaka Kudo, Hiroaki Takikawa, Takahiro Sakuragi
  • Publication number: 20120228261
    Abstract: There is provided a VUV light processing apparatus that can apply vacuum ultraviolet light to the entire surface of a wafer in excellent reproducibility and can process the wafer with VUV (vacuum ultraviolet) light in excellent reproducibility. A VUV light processing apparatus includes: a chamber connected with a gas supply apparatus and an evacuation apparatus, the chamber being capable of reducing the pressure inside the chamber; a plasma light source that generates VUV light including a wavelength of 200 nm or less, the plasma light source including a plasma generating unit that generates plasma in the chamber; and a VUV transmission filter provided between a stage on which a sample to be processed is placed and the sample in the chamber, the VUV transmission filter transmitting the VUV light including a wavelength of 200 nm or less and not transmitting electrons, ions, and radicals in plasma, the VUV transmission filter having the outer diameter size larger than that of the sample.
    Type: Application
    Filed: November 16, 2010
    Publication date: September 13, 2012
    Inventors: Seiichi Watanabe, Yutaka Kozuma, Tooru Aramaki, Naoki Yasui, Norihiko Ikeda, Hiroaki Takikawa
  • Publication number: 20120093617
    Abstract: A vacuum processing apparatus including a processing chamber for processing a sample to be processed, a cooling chamber for cooling the high-temperature sample processed in the processing chamber, and a vacuum transfer chamber for establishing a connection between the processing chamber and the cooling chamber, a vacuum transfer robot equipped inside the vacuum transfer chamber, wherein the cooling chamber includes a gas-exhausting unit for reducing pressure inside the cooling chamber, a gas-supplying unit for supplying a gas into the cooling chamber, a pressure-controlling unit for controlling the pressure inside the cooling chamber, a supporting unit for supporting the high-temperature sample, and a mounting stage for proximity-holding the sample supported by the supporting unit, the mounting stage having a temperature-adjusting unit for adjusting the temperature of surface of the mounting stage into a temperature which is capable of cooling the high-temperature sample, the supporting unit having an ascendi
    Type: Application
    Filed: January 21, 2011
    Publication date: April 19, 2012
    Inventors: Yutaka Kudou, Hiroaki Takikawa, Takahiro Shimomura, Masakazu Isozaki, Takashi Uemura
  • Patent number: 6969683
    Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: November 29, 2005
    Assignee: LSI Logic Corporation
    Inventors: Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay Dou, Sarah Neuman, Philippe Schoenborn, Keith Chao, Dilip Vijay, Kai Zhang, Masaichi Eda
  • Publication number: 20040161927
    Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 19, 2004
    Applicant: LSI Logic Corporation
    Inventors: Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay Dou, Sarah Neuman, Philippe Schoenborn, Keith Chao, Dilip Vijay, Kai Zhang, Masaichi Eda
  • Patent number: 6713386
    Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 30, 2004
    Assignee: LSI Logic Corporation
    Inventors: Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay Dou, Sarah Neuman, Philippe Schoenborn, Keith Chao, Dilip Vijay, Kai Zhang, Masaichi Eda
  • Patent number: 6686272
    Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Sang-Yun Lee, Masaichi Eda, Hongqiang Lu, Wei-Jen Hsia, Wilbur G. Catabay, Hiroaki Takikawa, Yongbae Kim