Abstract: A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

Abstract: A driving circuit includes a voltage converting circuit receiving a block selection signal and converting to a signal of a boosted potential level, and first and second N channel MOS transistors connected in series between the boosted potential and the ground potential. The gate of the first transistor receives the boosted potential, and a potential level at a connection node between the first and second transistors is provided as a signal BLI (i, 0).

Abstract: In a three-state circuit issuing a shared gate signal, after an N-channel MOS transistor charges a node issuing an output signal OUT to external power supply potential exvdd, the N-channel MOS transistor is turned off, and a P-channel MOS transistor is turned on to charge the node to boosted potential VPP. Thereby, a power consumed at boosted potential VPP can be reduced, and sizes of transistors of a VPP generating circuit can be reduced. Thereby, a semiconductor memory device having a small chip size can be achieved.

Abstract: A write control circuit of a DRAM core cell includes a sense amplifier and first to third N channel MOS transistors. The first and third MOS transistors constitute a column selection gate. If data “1” is written, a write mask signal and a data line are set at L level to render the second MOS transistor nonconductive. If data “0” is written, the write mask signal and the data line are set respectively at L and H levels to render the second MOS transistor conductive. In order to inhibit data rewriting, the write mask signal and the data line are both set at H level to render the second and third transistors nonconductive. Layout area and power consumption can be reduced compared with the conventional approach which requires two data lines.

Abstract: A read amplifier circuit includes an equalize start circuit. Based on a preamp enable signal PAE and an equalize signal IOEQ, the equalize start circuit generates an equalize start signal EQ for starting equalization at the timing when the preamp enable signal PAE is activated. Simultaneously with activation of a preamplifier by the preamp enable signal PAE, a pair of read lines GIOR and /GIOR is cut off from the preamplifier, and a P channel MOS transistor starts equalization of the pair of read lines GIOR and /GIOR. In this way, it is possible to start equalization of the paired read lines at the same time that the output signal is supplied to the preamplifier.

Abstract: The semiconductor memory device separates data input/output lines into a pair of write data lines and a pair of read data lines. A write gate is turned on with a column selection signal for writing, and a read gate is turned on with a column selection signal for reading. The pair of write data lines are not precharged but only the pair of read data lines are precharged in a transition to each operation. The pair of write data lines are precharged with a write mask signal in write masking. Thus, high-speed data processing is implemented.

Abstract: Disclosed are methods of safely producing a high quality negative electrode material composed of a mixture of a non-carbon material and a carbon material, a negative electrode using the negative electrode material, and a non-aqueous electrolyte battery using the negative electrode. The high quality negative electrode is produced by pulverizing and classifying each of the non-carbon material and the carbon material in an inert gas atmosphere, and further mixing them to each other in an inert gas atmosphere.

Abstract: A material for a negative electrode capable of preventing change in the volume of an active material occurring when lithium is doped/dedoped to improve resistance against cycle operations. A material for a negative electrode contains a mixture of a non-carbon material and a carbon material, wherein when an assumption is made that the average particle size of the non-carbon material is RM and the average particle size of the carbon material is RC, the ratio RM/RC is not higher than one, and when an assumption is made that the weight of the non-carbon material is WM and the weight of the carbon is WC, the ratio WM/WC is not higher than one or a mixture of a silicon compound and a carbon material, wherein when an assumption is made that the average particle size of the silicon compound is RSi and the average particle size of the carbon material is RC, the ratio RSi/RC is not higher than one.

Abstract: A transistor and a Pch circuit are connected in parallel to a power supply node of a CMOS circuit for receiving a power supply potential therefore. A transistor and an Nch circuit are connected in parallel to a ground node of the CMOS circuit for receiving a ground potential. During operation, the transistors are on, and the CMOS circuit operates fast. During standby, the Nch circuit or the Pch circuit is off in accordance with the state immediately before the standby. The Nch and Pch circuits are formed of transistors having larger threshold voltages than that of transistors of the CMOS circuit, so that a sub-threshold current during standby can be reduced.

Abstract: In a DRAM with an antifuse for programming a defective address, the antifuse and one electrode of a capacitor are connected to a shared node and the other electrode of the capacitor receives a boost signal. To blow the antifuse, the shared node is set high. To maintain the antifuse unblown, the shared node is set low. Then the boost signal is raised high to boost the shared node. Even when the resistance value of antifuse 1 is decreased, excessive current does not flow. This eliminates the necessity of providing a protection circuit as conventional and thus reduces circuit scale.

Abstract: First and second pairs of input/output lines transfer mutually complementary data signals respectively. First and second selection circuits select a signal transfer line having the same potential as that of a signal transfer line not precedently selected from two precedently selected signal transfer lines among first to third signal transfer lines and the signal transfer line not precedently selected and connect first ends thereof to the first pair of input/output lines respectively while connecting second ends thereof to the second pair of input/output lines respectively. Thus, no precharging may be performed for equalizing the potentials of the two signal transfer lines selected for present data transfer with each other, and hence reduction of a data transfer rate can be prevented.

Abstract: In a synchronous semiconductor memory device of the present invention, a main word driver and a sub decode driver have a function to take in a row decode signal in response to activation of a bank and to maintain the state of the row decode signal. Accordingly, of the circuits associated with row selection, a row pre-decoder, a row decoder and a row system control circuit can operate under a hierarchical power supply structure.