Abstract: An image decoding apparatus and an image decoding method capable of generating a decoded image even in the case where a pixel in a block is necessary as a reference pixel, the block where an intra prediction mode specified in a stream is unavailable according to a standard, due to a transmission error, a coding-method error, or the like. An image decoding apparatus determines whether or not a reference block necessary for a specified intra prediction mode is available, based on intra-prediction mode information extracted by an intra-prediction mode extraction unit and peripheral block pixel information stored in a line memory. The image decoding apparatus includes a reference pixel determination unit which controls a switch unit; and a substitute intra-prediction image generation unit which generates a substitute intra-prediction image in the case where a reference block necessary for a specified intra prediction mode is unavailable.

Abstract: There is disclosed a decoding method for decoding an incoming bitstream entropy-encoded according to an encoding method based on either of arithmetic encoding algorithm and non-arithmetic encoding algorithm, the incoming bitstream including syntax elements. The decoding method includes a first converting step of converting the incoming bitstream into an intermediate bitstream according to the encoding method, the first converting being capable of being omitted, a buffering step of selecting, according to the encoding method, either the intermediate bitstream or the incoming bitstream to store the selected bitstream onto a memory, and a second converting step of reading the selected bitstream from the memory to convert the read bitstream into syntax elements, the read bitstream being either the intermediate bitstream or the incoming bitstream.

Abstract: An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.

Abstract: An image decoding device and an encoding device include an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing.

Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.

Abstract: A motion compensation apparatus reduces the number of pixels for reading out pixel data from the multi-frame memory, and realizes the reduction of transmission and motion compensation in sub-pixel precision pixel generation, for efficient motion compensation pixel generation. The motion compensation apparatus includes a frame memory transmission control unit which, with regard to a plurality of motion compensation blocks, transmits reference pixels required in motion compensation collectively or on a per motion compensation block basis, from a multi-frame memory which stores a reference picture used in inter-picture motion compensation prediction, to a local reference memory.

Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.

Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.

Abstract: A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data.

Abstract: A decoding-processing apparatus (1) comprising: a context-calculating unit (2) operable to calculate the probability of symbols contained in incoming bitstreams; a parameter-generating unit (3) operable to generate parameters for use in the context-calculating unit (2); an arithmetic decoding-calculating unit (4) operable to decode the incoming bitstreams in accordance with the probability, thereby providing decoded data; a stream-converting unit (5) operable to convert the decoded data into intermediate bitstreams; a storage unit (6) operable to store the intermediate bitstreams; a synchronization-detecting unit (7) operable to detect calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing; and a multivalued calculating unit (8) operable to permit the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7

Abstract: An image decoding apparatus and an image decoding method capable of generating a decoded image even in the case where a pixel in a block is necessary as a reference pixel, the block where an intra prediction mode specified in a stream is unavailable according to a standard, due to a transmission error, a coding-method error, or the like. An image decoding apparatus (200) determines whether or not a reference block necessary for a specified intra prediction mode is available, based on intra-prediction mode information extracted by an intra-prediction mode extraction unit (102) and peripheral block pixel information stored in a line memory (104). The image decoding apparatus (200) includes a reference pixel determination unit (201) which controls a switch unit (202); and a substitute intra-prediction image generation unit (203) which generates a substitute intra-prediction image in the case where a reference block necessary for a specified intra prediction mode is unavailable.

Abstract: An image decoding device and an image encoding device according to the present invention includes an arithmetic unit for performing arithmetic processing, an arithmetic data storage unit for storing an arithmetic result by the arithmetic unit, an input selection unit for selecting whether to read pixel data that is to be inputted to the arithmetic unit from compressed image data or from pixel data stored in the arithmetic data storage unit, and inputting the read pixel data to the arithmetic unit, and an arithmetic control unit for controlling, based on a transform mode used and the number of arithmetic operations in the arithmetic unit, a destination from which the pixel data that is to be inputted to the arithmetic unit by the input selection unit is read as well as a combination of pieces of pixel data targeted for the arithmetic processing by the arithmetic unit and multiplier coefficients for the arithmetic processing, the arithmetic control unit previously defining an arithmetic procedure in each transf

Abstract: An object of the present invention is to provide a recording/reproduction terminal having a general-purpose slot and a detachable encoding or decoding device. A recording/reproduction device includes: a recording/reproduction terminal 103 which records and reproduces signals representing audio or video; and a removable coding device 100 which is detachably connected to the recording/reproduction terminal 103, and the recording/reproduction terminal 103 has a terminal information storage unit 105 which stores terminal information which is information regarding the recording/reproduction terminal 103, and a removable coding device 100 has: a terminal information obtainment unit 101 which obtains the terminal information from the recording/reproduction terminal 103 when the removable coding device 100 is connected to the recording/reproduction terminal 103; and a signal conversion unit 102 which encodes or decodes the signals representing audio or video based on the obtained terminal information.

Abstract: A multiplexed data producing apparatus which multiplexes N (integer) pieces of object data in which one of video data, audio data, and digital data is multiplexed to produce one piece of multiplexed data comprises a temporal storage means for temporarily storing the N pieces of object data; a control means for controlling synchronization of time information of each object data for each temporarily stored object data; and a multiplexing means for multiplexing the processed object data to produce multiplexed data.

Abstract: A moving picture is provided which can prevent image quality deterioration due to drops in motion vector prediction accuracy in temporal direct mode coding, and compress a moving image with great efficiency.

Abstract: A motion compensation apparatus is provided, which can reduce the number of pixels for reading out pixel data from the multi-frame memory, and can realize the reduction of transmission and motion compensation in sub-pixel precision pixel generation, for efficient motion compensation pixel generation. The motion compensation apparatus includes a frame memory transmission control unit which, with regard to a plurality of motion compensation blocks, transmits reference pixels required in motion compensation collectively or on a per motion compensation block basis, from a multi-frame memory which stores a reference picture used in inter-picture motion compensation prediction, to a local reference memory.

Abstract: An arithmetic decoding device comprises an adaptive arithmetic decoding unit, a context calculating unit, and a decoding control unit. The adaptive arithmetic decoding unit includes an arithmetic decoding unit, a symbol appearing probability control unit, and a probability state storing unit. When a variable-length encoded code (VLC) is inputted, the context calculating unit generates a context number from a classification and a decoded bit number of a syntax element of the inputted code, and outputs the context number to the adaptive arithmetic decoding unit. The adaptive arithmetic decoding unit renews a symbol appearing probability based on the frequency of appearance of the symbol, thereby arithmetic-decoding the inputted code (VLC), and feeding output data (OD). The decoding control unit controls the whole arithmetic decoding device.

Abstract: A decoding LSI adaptable to MPEG4 is provided with a padding means for performing padding on decoded texture data, an arithmetic decoding means for performing arithmetic decoding on coded shape data, and a composition means for compositing a plurality of texture data to generate composite image data. The padding means, the arithmetic decoding means, and the composition means are implemented by hardware circuits, i.e., a padding engine, an arithmetic decoding engine, and a composition engine, respectively. Therefore, the decoding LSI can perform high-speed decoding on a bitstream corresponding to plural objects, such as images, which are compressively coded by the MPEG4 coding method, with reduced cost of the hardware circuits performing the decoding process.

Abstract: A multiplexed data producing apparatus which multiplexes N (integer) pieces of object data in which one of video data, audio data, and digital data is multiplexed to produce one piece of multiplexed data comprises a temporal storage means for temporarily storing the N pieces of object data; a control means for controlling synchronization of time information of each object data for each temporarily stored object data; and a multiplexing means for multiplexing the processed object data to produce multiplexed data.

Abstract: A decoding LSI adaptable to MPEG4 is provided with a padding means for performing padding on decoded texture data, an arithmetic decoding means for performing arithmetic decoding on coded shape data, and a composition means for compositing a plurality of texture data to generate composite image data. The padding means, the arithmetic decoding means, and the composition means are implemented by hardware circuits, i.e., a padding engine, an arithmetic decoding engine, and a composition engine, respectively. Therefore, the decoding LSI can perform high-speed decoding on a bitstream corresponding to plural objects, such as images, which are compressively coded by the MPEG4 coding method, with reduced cost of the hardware circuits performing the decoding process.