Patents by Inventor Hiroaki TOKUYA
Hiroaki TOKUYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948986Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.Type: GrantFiled: June 16, 2021Date of Patent: April 2, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsushi Kurokawa, Masahiro Shibata, Hiroaki Tokuya, Mari Saji
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Publication number: 20230395542Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventors: Kazuya KOBAYASHI, Atsushi KUROKAWA, Hiroaki TOKUYA, Isao OBU, Yuichi SAITO
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Patent number: 11735541Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.Type: GrantFiled: June 26, 2019Date of Patent: August 22, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuya Kobayashi, Atsushi Kurokawa, Hiroaki Tokuya, Isao Obu, Yuichi Saito
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Patent number: 11601102Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.Type: GrantFiled: February 5, 2021Date of Patent: March 7, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hiroaki Tokuya, Hideyuki Sato, Fumio Harima, Kenichi Shimamoto, Satoshi Tanaka, Takayuki Kawano, Ryoki Shikishima, Atsushi Kurokawa
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Patent number: 11532736Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: GrantFiled: March 1, 2021Date of Patent: December 20, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
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Patent number: 11469187Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.Type: GrantFiled: July 30, 2020Date of Patent: October 11, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Masahiro Shibata, Akihiko Ozaki, Satoshi Goto, Fumio Harima, Atsushi Kurokawa
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Patent number: 11404357Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.Type: GrantFiled: January 22, 2020Date of Patent: August 2, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsushi Kurokawa, Hiroaki Tokuya, Kazuya Kobayashi, Yuichi Sano
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Publication number: 20220157748Abstract: A mounting substrate has one main surface (a first main surface). An electronic component has a first face, a second face, and a side face, and is provided on the one main surface of the mounting substrate. A solder bump is disposed between the mounting substrate and the electronic component, and electrically connects the mounting substrate and the electronic component. A resin layer is provided on the one main surface of the mounting substrate to cover the electronic component. The first face is a face of the electronic component at a side opposite to the mounting substrate. The side face of the electronic component is in contact with the resin layer. A space is provided between at least a part of the first face and the resin layer in a thickness direction of the mounting substrate.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Mayuka ONO, Motoji TSUDA, Fumio HARIMA, Koshi HIMEDA, Hiroaki TOKUYA
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Patent number: 11335617Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.Type: GrantFiled: January 16, 2020Date of Patent: May 17, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Yuichi Sano, Toshihiro Tada
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Publication number: 20210391429Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.Type: ApplicationFiled: June 16, 2021Publication date: December 16, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Atsushi KUROKAWA, Masahiro SHIBATA, Hiroaki TOKUYA, Mari SAJI
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Publication number: 20210242842Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.Type: ApplicationFiled: February 5, 2021Publication date: August 5, 2021Inventors: Hiroaki TOKUYA, Hideyuki SATO, Fumio HARIMA, Kenichi SHIMAMOTO, Satoshi TANAKA, Takayuki KAWANO, Ryoki SHIKISHIMA, Atsushi KUROKAWA
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Publication number: 20210184022Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
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Patent number: 10978579Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: GrantFiled: July 8, 2019Date of Patent: April 13, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
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Publication number: 20210035922Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.Type: ApplicationFiled: July 30, 2020Publication date: February 4, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Hiroaki TOKUYA, Masahiro SHIBATA, Akihiko OZAKI, Satoshi GOTO, Fumio HARIMA, Atsushi KUROKAWA
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Publication number: 20200161226Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.Type: ApplicationFiled: January 22, 2020Publication date: May 21, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Atsushi KUROKAWA, Hiroaki TOKUYA, Kazuya KOBAYASHI, Yuichi SANO
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Publication number: 20200152536Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Yuichi Sano, Toshihiro Tada
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Patent number: 10559547Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.Type: GrantFiled: June 12, 2018Date of Patent: February 11, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Masahiro Shibata, Daisuke Tokuda, Atsushi Kurokawa, Hiroaki Tokuya, Yasunari Umemoto
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Publication number: 20200006265Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.Type: ApplicationFiled: June 26, 2019Publication date: January 2, 2020Inventors: Kazuya KOBAYASHI, Atsushi KUROKAWA, Hiroaki TOKUYA, Isao OBU, Yuichi SAITO
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Publication number: 20190333887Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
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Patent number: 10388623Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: GrantFiled: April 16, 2018Date of Patent: August 20, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya