Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device and a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device, in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b, and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b, and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the P type impurity region 13b and the P type well 13 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Certain embodiments of the present invention relate to a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer.

Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device and a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the connection layer 19 and the bit line 300 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Certain embodiments of the present invention relate to a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer.

Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+ type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the P type impurity region 13b and the P type well 13 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the connection layer 19 and the bit line 300 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device, in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b, and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b, and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: An integrated circuit wafer composed of a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, each chip having at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and the wafer further including at least one interlayer insulation film having portions which extend across each chip and interposed between two of the layers of electrically conductive material to form a component part of each element, the interlayer insulation film further having portions which extend across the scribe lines at the time the substrate is cut along the scribe lines and which are contiguous with portions of the interlayer insulation film that extend across each chip, wherein the wafer is provided with one or more defined patterns located at at least one scribe line region and a passivati

Abstract: A semiconductor device wafer in which the interlayer insulating film between wirings and the passivation film formed during the manufacturing process are left on the entire surface of the scribe line area during dicing. The interlayer insulating film between wirings and the passivation film formed during the manufacturing process may be left on most of the scribe line area, in which case a slit groove is provided along the periphery of a chip and the passivation film is removed at the location of the slit groove. Alternatively, the passivation film formed during the manufacturing process may be left on a part of the scribe line area where a film structure is provided.