Patents by Inventor Hiroaki Tsutsui

Hiroaki Tsutsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040044475
    Abstract: A case base (54) as one of nonlinear black box prediction models is generated from historical data containing inflow data (31) that indicates a sewage inflow measured at a sewage treatment plant (10) and meteorological data (33) corresponding to the inflow data (31). A similar case search section (56) and output estimation section (57) predict a sewage inflow corresponding to an input prediction condition (40) after a predetermined prediction time in real time using the case base (54) and output inflow prediction data (20).
    Type: Application
    Filed: August 12, 2003
    Publication date: March 4, 2004
    Inventors: Toshiaki Oka, Hiroaki Tsutsui
  • Publication number: 20040005120
    Abstract: A connection structure of a light transfer medium includes: a light transfer medium embedded in a structural body; and a protection tube in which the light transfer medium is inserted. The protection tube is embedded in the structural body at one end portion of the structural body. One end portion of the light transfer medium is inserted into the protection tube such that an end of the one end portion of the light transfer medium is positioned inwardly from one end face of the one end portion of said structural body.
    Type: Application
    Filed: April 15, 2003
    Publication date: January 8, 2004
    Applicant: R & D Institute of Metals and Composites for Future Industries
    Inventors: Nobuo Takeda, Hiroaki Tsutsui, Akio Kawamata
  • Patent number: 6510245
    Abstract: When n-dimensional data which belongs to one class in an n-dimensional feature space defined by n types of variates and whose position is specified by the variates is input, the feature space is divided into mn divided areas by performing m-part division for each of the variates. In this division, a division number m is determined on the basis of a statistical significance level by regarding a degree of generation of a divided area containing one data as a degree following a probability distribution with respect to the division number m. A classification model is generated by classifying the generated divided areas depending on whether they contain n-dimensional data.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: January 21, 2003
    Assignee: Yamatake Corporation
    Inventor: Hiroaki Tsutsui
  • Publication number: 20030012934
    Abstract: A polymer gel composition and an optical element using the same are provided. The polymer gel composition has a simple constitution, can be applied for a display element of transmission type, and exhibits large differences in the light-scattering index, light refractive index, and light absorption according to an imposed electric field with stable repeating performance. The polymer gel composition and the optical element using it contain a liquid and a charged polymer gel that exhibits volumetric change depending on the absorption/releasing of the liquid according to an imposed electric field.
    Type: Application
    Filed: March 13, 2002
    Publication date: January 16, 2003
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Jun Kawahara, Hiroaki Tsutsui, Masato Mikami, Ryojiro Akashi
  • Publication number: 20020043655
    Abstract: Described is an optical element having plural electrodes and, disposed therebetween, a stimuli-responsive polymer gel, a liquid which can be absorbed therein and an ion supplying material. As the ion supplying material, preferred is a material showing a volumetric change, in the form of the element, of 0 to 100% under external stimuli. According to the present invention, a novel optical element showing a large change in light transmittance, reflectance or absorption amount and exhibits stable optical properties in repetition can be provided.
    Type: Application
    Filed: March 7, 2001
    Publication date: April 18, 2002
    Applicant: Fuji Xerox Co. Ltd.
    Inventors: Takashi Uematsu, Akinori Komura, Hiroaki Tsutsui, Jun Kawahara, Masato Mikami, Ryojiro Akashi
  • Patent number: 6239623
    Abstract: In a DCFL circuit, a high-speed operation is conducted in a stable state regardless of its load capacitance. The circuit includes a buffer circuit. Added to the buffer circuit is a pull-up circuit conducting a pull-up operation for a predetermined period of time when an output potential of the circuit changes from a low level to a high level. A first EFET of the pull-up circuit includes a gate electrode connected to an output terminal of a logic stage, a drain electrode coupled with a positive power source, and a source electrode linked with a drain of a second EFET. The second EFET includes a gate electrode connected to a node linked in series to a resistor element. The resistor is coupled with an input terminal. The second EFET includes the drain electrode connected to a source electrode of the first EFET and a source electrode linked with an output terminal.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventor: Hiroaki Tsutsui
  • Patent number: 5925901
    Abstract: A GaAs substrate is divided at boundary regions of unit cells of FET chips. With such construction, magnitude of curling of the GaAs substrate due to a difference of thermal expansion coefficients between the GaAs substrate and the PHS upon heating during assembling, can be reduced. In a semiconductor device with a PHS, the magnitude of curling of the semiconductor substrate after assembling can be reduced by reducing stress upon assembling, without causing degradation of reliability.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventor: Hiroaki Tsutsui
  • Patent number: 5922623
    Abstract: Disclosed is a method selective of vapor phase etching for fabricating a semiconductor device having a refractory metal silicide electrode abutting a silicon oxide film on the surface or a semiconductor device having an AlGaAs layer, an electrode formed on the AlGaAs layer and a silicon oxide film on the surface of the semiconductor device. The method comprises a step of removing a portion of the silicon oxide film by a gas including a vapor of hydrogen fluoride. The method further uses a mixture of nitrogen gas including vapor of anhydrous hydrofluoric acid and a nitrogen gas including a vapor of H.sub.2 O, wherein the ratio of the nitrogen gas including the vaporized anhydrous hydrofluoric acid to the nitrogen gas including vapor of H.sub.2 O is less than 1.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: July 13, 1999
    Assignee: NEC Corporation
    Inventors: Hiroaki Tsutsui, Takao Matsumura, Hirokazu Oikawa, Masayuki Yokoi, Junichi Nakamura, Hiroyuki Sato, Jun Mizoe
  • Patent number: 5918200
    Abstract: In a state estimating apparatus, an input space quantization section quantizes an input space according to a required precision of output data. A storage section calculates and stores the number of times of occurrence of output data corresponding to each input event in the quantized input space, the mean values of the output data, and the change amounts of the output data. A neighborhood definition section calculates an input space neighborhood satisfying the required precision of the output. A similar case extraction section zooms up the predetermined neighborhood of the input space to the predetermined degree and extracts input case similar to the neighborhood from input case in the input space. A similarity determination section determines the similarity between the new input event and the extracted similar input cases on the basis of the degree of zooming.
    Type: Grant
    Filed: August 19, 1993
    Date of Patent: June 29, 1999
    Assignee: Yamatake-Honeywell Co., Ltd.
    Inventors: Hiroaki Tsutsui, Atsushi Kurosaki, Kazuyuki Kamimura, Tadahiko Matsuba
  • Patent number: 5821154
    Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: October 13, 1998
    Assignee: NEC Corporation
    Inventors: Yasunobu Nashimoto, Hiroaki Tsutsui
  • Patent number: 5726494
    Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: March 10, 1998
    Assignee: NEC Corporation
    Inventors: Yasunobu Nashimoto, Hiroaki Tsutsui
  • Patent number: 5698897
    Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: December 16, 1997
    Assignee: NEC Corporation
    Inventors: Yasunobu Nashimoto, Hiroaki Tsutsui
  • Patent number: 5504352
    Abstract: In a recessed structure MESFET, an active layer (n-type layer) 2 is provided on a high resistance GaAs substrate 1, a pair of contact layers (n.sup.+ -type layers) 31, 32 is provided on the active layer 2, a source electrode 6 is provided on one contact layer 31, a drain electrode 7 is provided on the other contact layer 32 and a gate electrode 5 is provided on the active layer 2 to achieve a recessed structure. A semiconductor layer 4 having a lower impurity density than that of the contact layer 31, 32 is formed at the recess edge portion at at least drain side to alleviate the concentration of the electric field and current there to suppress the generation of electron-holes pairs by collision ionization to reduce the damage to the crystal lattice by non-luminescence recombination of the electron-holes thus preventing the degradation of the FET characteristics.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: April 2, 1996
    Assignee: NEC Corporation
    Inventors: Hiroaki Tsutsui, Akira Mochizuki
  • Patent number: 5157632
    Abstract: A sense amplifier circuit is provided in association with a column of memory cells through first and second bit lines for increasing a small difference in voltage level between the first and second bit lines and comprises first and second series combinations of field effect transistors coupled in parallel between a power voltage level and a discharging transistor, in which an auxiliary current path is established in parallel to a main current path produced in the second series combination while the small difference is increased, thereby accelerating the increasing operation of the small difference without any sacrifice of current consumption in the idling stage.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: October 20, 1992
    Assignee: NEC Corporation
    Inventor: Hiroaki Tsutsui
  • Patent number: 4985645
    Abstract: A BiCMOS logic circuit includes a MOS logic circuit connected between a high voltage supply line and a low voltage supply line and having an input connected to an input terminal, and an output circuit composed of first and second bipolar transistors connected in series between the high and low voltage supply lines. The first bipolar transistor has a base connected to an output of the MOS logic circuit, and a connection node of the first and second bipolar transistors is connected to an output terminal. In addition, a base current supplying circuit having first and second MOS transistors is connected in series between the first voltage supply line and a base of the second bipolar transistor. The first MOS transistor has a gate connected to the output of the MOS logic circuit, and the second MOS transistor has a gate connected to the input terminal.
    Type: Grant
    Filed: September 26, 1989
    Date of Patent: January 15, 1991
    Assignee: NEC Corporation
    Inventor: Hiroaki Tsutsui