Patents by Inventor Hiroaki Yamanaka

Hiroaki Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11846317
    Abstract: In a tapered roller bearing, the surface roughness of at least a rolling surface and a large diameter-side end surface of a tapered roller is 0.02 to 0.17 ?m in protruding mountain portion height Rpk, 0.12 to 0.21 ?m in core portion level difference Rk, and 0.07 to 0.43 ?m in protruding valley portion height Rvk and the average recessed portion area in the fine irregularities on the surface of the tapered roller is 5 ?m2 or less. As a result, oil film formability can be improved under dilute lubrication and a decline in lubricating oil viscosity and surface damage at a rolling contact part and an increase in friction at a sliding contact part can be suppressed at the same time.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 19, 2023
    Assignee: NSK LTD.
    Inventors: Masaki Chishima, Hiroaki Yamanaka, Hiroyuki Ohshima
  • Publication number: 20220390431
    Abstract: A device for blood (1) is provided with a column (50) and a micro flow path (20) located downstream of the column (50). The column (50) includes a porous material as a solid phase, and blood that has contacted with the porous material flows through the micro flow path (20). In the device for blood (1), the column (50) and the micro flow path (20) are provided as separated bodies. The column (50) has a connecting part (55), the micro flow path (20) has an inlet (21a), the connecting part (55) and the inlet (21a) are connected to each other to integrate the column (50) with the micro flow path (20), and blood (BL) is allowed to pass from the column (50).
    Type: Application
    Filed: October 15, 2020
    Publication date: December 8, 2022
    Inventors: Tomohiro KUBO, Hiroaki YAMANAKA
  • Publication number: 20220196065
    Abstract: In a tapered roller bearing (10), the surface roughness of at least a rolling surface (13c) and a large diameter-side end surface (13b) of a tapered roller (13) is 0.02 to 0.17 ?m in reduced peak height Rpk, 0.12 to 0.21 ?m in core roughness depth Rk, and 0.07 to 0.43 ?m in reduced valley depth Rvk and the average recessed portion area in the fine irregularities on the surface of the tapered roller (13) is 5 ?m2 or less. As a result, oil film formability can be improved under dilute lubrication and a decline in lubricating oil viscosity and surface damage at a rolling contact part and an increase in friction at a sliding contact part can be suppressed at the same time.
    Type: Application
    Filed: March 19, 2020
    Publication date: June 23, 2022
    Applicant: NSK LTD.
    Inventors: Masaki CHISHIMA, Hiroaki YAMANAKA, Hiroyuki OHSHIMA
  • Patent number: 11306774
    Abstract: A holder of a tapered roller bearing is made of a resin, has a first gap between an axially inner end surface of a small-diameter-side annular part and small-diameter-side end surfaces of tapered rollers, has a second gap between an axially inner end surface of a large-diameter-side annular part and large-diameter-side end surfaces of the tapered rollers, and is provided to be capable of moving within a prescribed range along the axial direction. The surface of the axially inner end surface of the large-diameter-side annular part is rough, the large-diameter-side annular part is provided with one or more grooves which are oil-holding parts that hold the lubricating oil, and ends of the grooves are positioned to be capable of coming into contact with the tapered rollers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 19, 2022
    Assignee: NSK LTD.
    Inventors: Makoto Zembutsu, Hiroaki Yamanaka, Tomoyuki Miyazaki, Hiroki Maejima
  • Publication number: 20210382035
    Abstract: Blood containing cells is brought into contact with a porous surface of a porous material before classification of the cells in the blood by flowing the blood through a microchannel. In an example, the porous material is added to the blood containing the cells and mixed together, thereby bringing the blood containing the cells into contact with the porous surface. In an example, the porous material has particles with the porous surface including polysaccharides. The porous material is added to the blood containing the cells while being suspended in a liquid. In an example, the particles have a predetermined particle size distribution. A median particle size d50V in the volume-based cumulative distribution is 25 to 280 ?m.
    Type: Application
    Filed: September 26, 2019
    Publication date: December 9, 2021
    Applicant: TL Genomics Inc.
    Inventors: Tomohiro KUBO, Tomoyuki KANEIWA, Hiroaki YAMANAKA, Ryohei SEKI
  • Publication number: 20210054877
    Abstract: A holder of a tapered roller bearing is made of a resin, has a first gap between an axially inner end surface of a small-diameter-side annular part and small-diameter-side end surfaces of tapered rollers, has a second gap between an axially inner end surface of a large-diameter-side annular part and large-diameter-side end surfaces of the tapered rollers, and is provided to be capable of moving within a prescribed range along the axial direction. The surface of the axially inner end surface of the large-diameter-side annular part is rough, the large-diameter-side annular part is provided with one or more grooves which are oil-holding parts that hold the lubricating oil, and ends of the grooves are positioned to be capable of coming into contact with the tapered rollers.
    Type: Application
    Filed: March 8, 2019
    Publication date: February 25, 2021
    Applicant: NSK LTD.
    Inventors: Makoto ZEMBUTSU, Hiroaki YAMANAKA, Tomoyuki MIYAZAKI, Hiroki MAEJIMA
  • Patent number: 7952410
    Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: May 31, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroaki Yamanaka, Kunimitsu Kousaka, Kiyoshi Nishiwaki
  • Patent number: 7788573
    Abstract: A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: August 31, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroaki Yamanaka
  • Patent number: 7622959
    Abstract: It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference between the comparison target signals COMP1 and COMP2 to the control terminal of a tri-state buffer, based on a signal synchronous with the start-up of the comparison target signal COMP1 detected by an edge detection flag generation circuit and a signal synchronous with the start-up of the comparison target signal COMP2 detected by an edge detection flag generation circuit. A status management circuit outputs a signal A_SIGNAL corresponding to the phase advance or delay of the comparison target signals COMP1 and COMP2 to the input terminal of the tri-state buffer.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: November 24, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Hiroaki Yamanaka
  • Patent number: 7551450
    Abstract: An external storage apparatus capable of preventing erroneous assembly of components for which the assembly position is decided and of suppressing the occurrence of variations in its quality is provided. An external storage apparatus including a main body 11, a memory substrate 12 having a connector 24, a substrate holder 13 for fixing the memory substrate 12 to the main body under the state that the connector 24 projects outward, a cap 14 to be attachable and detachable to and from the substrate holder 13 for protecting the connector 24, wherein erroneous assembly restricting means 38, 37, 40 and 32 are provided between the main body 11, the memory substrate 12 and the substrate holder 13.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: June 23, 2009
    Assignee: Sony Corporation
    Inventors: Norio Sugawara, Takashi Ando, Hiroaki Yamanaka
  • Publication number: 20080122471
    Abstract: A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part.
    Type: Application
    Filed: October 3, 2006
    Publication date: May 29, 2008
    Inventor: Hiroaki Yamanaka
  • Publication number: 20080074203
    Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.
    Type: Application
    Filed: November 20, 2007
    Publication date: March 27, 2008
    Inventors: Hiroaki Yamanaka, Kunimitsu Kousaka, Kiyoshi Nishiwaki
  • Patent number: 7315213
    Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: January 1, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroaki Yamanaka, Kunimitsu Kousaka, Kiyoshi Nishiwaki
  • Publication number: 20060132243
    Abstract: A voltage-controlled oscillation circuit (15) includes a plurality of independent ring oscillation circuits different in the number of stages; and a selector (22) selectively outputting as a feedback clock signal (FB) an output of one of the ring oscillation circuits, so that any of the outputs of the independent ring oscillation circuits is always outputted as the feedback clock signal, which makes it possible to output the feedback clock signal keeping a proper duty ratio even when the operating speed is high, allowing arbitrary adjustment of the delay time before an input signal (DLLI) is outputted.
    Type: Application
    Filed: February 16, 2006
    Publication date: June 22, 2006
    Inventors: Hiroaki Yamanaka, Kunimitsu Kousaka, Kiyoshi Nishiwaki
  • Publication number: 20060097755
    Abstract: It is an object of the present invention to improve the phase difference detection accuracy of a phase comparator. A phase difference signal generation circuit outputs a signal C_SIGNAL which takes a high level for a period corresponding to the phase difference between the comparison target signals COMP1 and COMP2 to the control terminal of a tri-state buffer, based on a signal synchronous with the start-up of the comparison target signal COMP1 detected by an edge detection flag generation circuit and a signal synchronous with the start-up of the comparison target signal COMP2 detected by an edge detection flag generation circuit. A status management circuit outputs a signal A_SIGNAL corresponding to the phase advance or delay of the comparison target signals COMP1 and COMP2 to the input terminal of the tri-state buffer.
    Type: Application
    Filed: March 10, 2005
    Publication date: May 11, 2006
    Inventor: Hiroaki Yamanaka
  • Publication number: 20050157462
    Abstract: An external storage apparatus capable of preventing erroneous assembly of components for which the assembly position is decided and of suppressing the occurrence of variations in its quality is provided. An external storage apparatus including a main body 11, a memory substrate 12 having a connector 24, a substrate holder 13 for fixing the memory substrate 12 to the main body under the state that the connector 24 projects outward, a cap 14 to be attachable and detachable to and from the substrate holder 13 for protecting the connector 24, wherein erroneous assembly restricting means 38, 37, 40 and 32 are provided between the main body 11, the memory substrate 12 and the substrate holder 13.
    Type: Application
    Filed: January 7, 2004
    Publication date: July 21, 2005
    Applicant: Sony Corporation
    Inventors: Norio Sugawara, Takashi Ando, Hiroaki Yamanaka
  • Patent number: 4391702
    Abstract: A method for classifying wet coal for obtaining coal charges suitable for use in a coke oven comprising classifying the wet coal directly in a cylindrical screen which rotates and revolves around an eccentric rotation shaft while blowing a high pressure gas stream to the screen to eliminate adhesion of the wet coal particles to the screen. The method enables a continuous and consistent classification of wet coals without the clogging of the screen and the dust pollution. The cokes obtained by dry distillation of the coal classified by the present method show high quality.
    Type: Grant
    Filed: October 7, 1981
    Date of Patent: July 5, 1983
    Assignee: Nippon Steel Corporation
    Inventors: Shozo Murakami, Hiroaki Yamanaka, Kazuhiro Yokoyama, Yasuhiro Yone, Tokuji Yamaguchi
  • Patent number: 4310412
    Abstract: A method for classifying wet coal for obtaining coal charges suitable for use in a coke oven comprising classifying the wet coal directly in a cylindrical screen which rotates and revolves around an eccentric rotation shaft while blowing a high pressure gas stream to the screen to eliminate adhesion of the wet coal particles to the screen. The method enables a continuous and consistent classification of wet coals without the clogging of the screen and the dust pollution. The cokes obtained by dry distillation of the coal classified by the present method show high quality.
    Type: Grant
    Filed: September 7, 1979
    Date of Patent: January 12, 1982
    Assignee: Nippon Steel Corporation
    Inventors: Syozo Murakami, Hiroaki Yamanaka, Kazuhiro Yokoyama, Yasuhiro Yone, Tokuzi Yamaguchi