Abstract: According to one embodiment, a circuit noise determination system includes a reading unit that reads a netlist representing a target circuit and analysis settings for noise analysis. A noise calculation unit is provided in the system to calculate noise values of circuit elements of in the target circuit according to the netlist along with a circuit classification unit that identifies and classifies circuit element in the target circuit. The system further includes a noise determination unit that outputs a notification regarding elements exceeding a noise upper limit reference value set based on a plurality of noise determinations prepared in advance for each circuit classification.

Abstract: According to one embodiment, a solid-state imaging device is configured as follows. A pixel array portion is configured such that pixels storing photoelectrically converted charge are arranged in an m (m is a positive integer) by n (n is a positive integer) matrix. A column ADC circuit calculates, for each column, an AD-converted value of a pixel signal read from the pixel based on a comparison result between the pixel signal and a reference voltage. The redundant column ADC circuit can relieve each column of the column ADC circuit. The column selection circuit can make a selection for each column so that the pixel signal input to the column ADC circuit is also input to the redundant column ADC circuit.

Abstract: According to one embodiment, there is provided a solid-state imaging device in which vertical signal lines VL1-1, VL1-2, VL2-1, VL2-2, VL3-1, and VL3-2 are respectively arranged between power lines DL1-1, DL1-3, DL2-1, DL2-3, DL3-1, and DL3-3, power lines DL1-2, DL2-2, and DL3-2 are respectively arranged between the vertical signal lines VL1-1, VL1-2, VL2-1, VL2-2, VL3-1, and VL3-2, power lines DL1-1 and DL1-3 are arranged to cross each other in each pixel in the column direction, power lines DL2-1 and DL2-3 are arranged to cross each other in each pixel in the column direction, and power lines DL3-1 and DL3-3 are arranged to cross each other in each pixel in the column direction.

Abstract: According to one embodiment, a pixel array unit has pixels for accumulating photoelectric-converted charges arranged in a matrix in a row direction and a column direction; a column ADC circuit calculates, based on results of comparison between pixel signals read from the pixels and a reference voltage, AD-converted values of the pixel signals in each of columns; vertical signal wires transmit the pixel signals read from the pixels in each of the columns to the column ADC circuit; and a load circuit is dispersed in the row direction and forms source follower circuits with the pixels to read pixel signals from the pixels in each of the columns to the vertical signal wires.

Abstract: According to one embodiment, a solid-state imaging device is configured as follows. A pixel array portion is configured such that pixels storing photoelectrically converted charge are arranged in an m (m is a positive integer) by n (n is a positive integer) matrix. A column ADC circuit calculates, for each column, an AD-converted value of a pixel signal read from the pixel based on a comparison result between the pixel signal and a reference voltage. The redundant column ADC circuit can relieve each column of the column ADC circuit. The column selection circuit can make a selection for each column so that the pixel signal input to the column ADC circuit is also input to the redundant column ADC circuit.

Abstract: According to one embodiment, a pixel array unit has pixels for accumulating photoelectric-converted charges arranged in a matrix in a row direction and a column direction; a column ADC circuit calculates, based on results of comparison between pixel signals read from the pixels and a reference voltage, AD-converted values of the pixel signals in each of columns; vertical signal wires transmit the pixel signals read from the pixels in each of the columns to the column ADC circuit; and a load circuit is dispersed in the row direction and forms source follower circuits with the pixels to read pixel signals from the pixels in each of the columns to the vertical signal wires.

Abstract: According to one embodiment, a solid-state imaging device includes a pixel array unit in which pixels for accumulating photoelectric-converted charges are arranged in a matrix of a row direction and a column direction; and a vertical scanning circuit in which drivers for driving the pixels are dispersed in each of rows.

Abstract: According to one embodiment, there is provided a solid-state imaging device in which vertical signal lines VL1-1, VL1-2, VL2-1, VL2-2, VL3-1, and VL3-2 are respectively arranged between power lines DL1-1, DL1-3, DL2-1, DL2-3, DL3-1, and DL3-3, power lines DL1-2, DL2-2, and DL3-2 are respectively arranged between the vertical signal lines VL1-1, VL1-2, VL2-1, VL2-2, VL3-1, and VL3-2, power lines DL1-1 and DL1-3 are arranged to cross each other in each pixel in the column direction, power lines DL2-1 and DL2-3 are arranged to cross each other in each pixel in the column direction, and power lines DL3-1 and DL3-3 are arranged to cross each other in each pixel in the column direction.

Abstract: According to one embodiment, a design method of a semiconductor integrated circuit is a design method of a semiconductor integrated circuit including a first wiring layer, a second wiring layer formed on the first wiring layer, and a third wiring layer formed on the second wiring layer. This method includes a process in which plural spare wirings are arranged on the second wiring layer along a first direction, and plural spare wirings are arranged on the third wiring layer in a second direction orthogonal to the first direction. The method also includes a process of arranging a cell on the first wiring layer after the arrangement of the spare wirings, a process of arranging a signal wiring on at least any one of the first to the third wiring layers after the arrangement of the cell, and a process of performing an engineering change order of the wiring by using the spare wirings.

Abstract: According to one embodiment, a design method of a semiconductor integrated circuit is a design method of a semiconductor integrated circuit including a first wiring layer, a second wiring layer formed on the first wiring layer, and a third wiring layer formed on the second wiring layer. This method includes a process in which plural spare wirings are arranged on the second wiring layer along a first direction, and plural spare wirings are arranged on the third wiring layer in a second direction orthogonal to the first direction. The method also includes a process of arranging a cell on the first wiring layer after the arrangement of the spare wirings, a process of arranging a signal wiring on at least any one of the first to the third wiring layers after the arrangement of the cell, and a process of performing an engineering change order of the wiring by using the spare wirings.

Abstract: Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.

Abstract: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.

Abstract: Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor cores with a corresponding operating clock signal. The timing system uses variable delay elements to impart variable delays to the clock signals. A delay management unit determines the delays that should be used by the task processing units in executing their assigned tasks and provides this information to the variable delay elements to set the appropriate delays in each of these elements. The delay information is also provided to a task management unit, which assigns the tasks to specific processor cores based upon the delays selected by the delay management unit, so that consecutively fired processor cores are not adjacent to each other.

Abstract: Systems and methods for improving the reliability of multiprocessors by reducing the aging of processor cores that have lower performance. One embodiment comprises a method implemented in a multiprocessor system having a plurality of processor cores. The method includes determining performance levels for each of the processor cores and determining an allocation of the tasks to the processor cores that substantially minimizes aging of a lowest-performing one of the operating processor cores. The allocation may be based on task priority, task weight, heat generated, or combinations of these factors. The method may also include identifying processor cores whose performance levels are below a threshold level and shutting down these processor cores. If the number of processor cores that are still active is less than a threshold number, the multiprocessor system may be shut down, or a warning may be provided to a user.

Abstract: Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.

Abstract: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.

Abstract: Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor cores with a corresponding operating clock signal. The timing system uses variable delay elements to impart variable delays to the clock signals. A delay management unit determines the delays that should be used by the task processing units in executing their assigned tasks and provides this information to the variable delay elements to set the appropriate delays in each of these elements. The delay information is also provided to a task management unit, which assigns the tasks to specific processor cores based upon the delays selected by the delay management unit, so that consecutively fired processor cores are not adjacent to each other.

Abstract: Aliphatic polyester copolymers, which have molecular weights high enough for practical use and which are excellent in thermal stability, tensile strength and moldability, and which are biodegradable as well, are provided, which are produced by a process comprising effecting polycondensation of an aliphatic diol and an aliphatic dicarboxylic acid in the presence of an aliphatic monohydroxymonocarboxylic acid in a specific amount and of a catalyst comprising a germanium compound.

Abstract: A copolymer having repeating units of the following formula (I) and repeating units of the formula (II), wherein the ration of (I) to (II) is within a range of from 10:90 to 90:10 by weight ratio, and the number average molecular weight is at least 1,000, or the intrinsic viscosity .eta..sub.inh is at least 0.02: ##STR1## wherein A is a polyester unit having a polymerization degree of from 2 to 200, R.sup.3 is a bivalent organic group having an ester, urethane or ketone bond, and R.sup.4 is a hydrogen atom or a methyl group, ##STR2## wherein R.sup.5 is a hydrogen atom or a methyl group, and X is a substituent having functionality.