Abstract: A display panel driver includes a scaler circuit performing image enlargement processing on input image data corresponding to an input image to generate ?-times enlarged image data corresponding to an ?-times enlarged image (?is a number larger than one which cannot be represented as 2k); and a driver section driving a display panel. In calculating a pixel value of a target pixel of the ?-times enlarged image, the scaler circuit generates enlarged image data including 2n-times enlarged image data corresponding to a 2n-times enlarged image obtained by enlarging the input image with an enlargement factor of 2n (n is the smallest integer determined so that 2n is larger than ?), and calculates the pixel value of the target pixel from the 2n-times enlarged image data through interpolation processing of pixel values of pixels of the 2n-times enlarged image corresponding to the target pixel of the ?-times enlarged image.

Abstract: A display driver includes gamma curve control circuitry and a converter controller. The gamma curve control circuitry is configured to generate a first gamma curve for a first display brightness value (DBV), and a second gamma curve for a second DBV lower than the first DBV. The converter controller is configured to control a digital-analog converter (DAC) configured to perform digital-analog conversion of an input image data.

Abstract: A host device divides original data into first to Nth stream data for N being an integer of two or more, generates first to Nth compressed stream data by sequentially compressing the first to Nth stream data with a variable length compression, divides the first to Nth compressed stream data into fixed-length blocks, and sequentially transmits the fixed-length blocks to the display driver. The display driver includes a memory storing therein the fixed-length blocks and a decompression circuitry reading out the fixed-length blocks from the memory. The decompression circuitry includes first to Nth processing circuits. The first to Nth processing circuits each perform a predetermined process on the fixed-length blocks received to generate processed data. The host device sorts the fixed-length blocks so that the fixed-length blocks are supplied in the order in which the first to Nth processing circuits require the fixed-length blocks.

Abstract: An image processing apparatus includes: a first circuit which calculates values f(RPi), f(GPi) and f(BPi) by applying a function f(x) to an R grayscale value RPi, a G grayscale value GPi and a B grayscale value BPi of each pixel i of a first image; a second circuit which calculates values f(RQi), f(GQi) and f(BQi) by applying the function f(x) to an R grayscale value RQi, a G grayscale value GQi and a B grayscale value BQi of each pixel i of a second image; and a similarity calculation circuit which calculates a degree of similarity between the first and second images depending on |f(RPi)?f(RQi)|, |f(GPi)?|f(GQi)| and |f(BPi)?f(BQi)| associated with each pixel i of the first and second images. The function f(x) is a convex function monotonically non-decreasing in the domain of definition.

Abstract: A display panel driver includes a scaler circuit performing image enlargement processing on input image data corresponding to an input image to generate ?-times enlarged image data corresponding to an ?-times enlarged image (? is a number larger than one which cannot be represented as 2k); and a driver section driving a display panel. In calculating a pixel value of a target pixel of the ?-times enlarged image, the scaler circuit generates enlarged image data including 2n-times enlarged image data corresponding to a 2n-times enlarged image obtained by enlarging the input image with an enlargement factor of 2n (n is the smallest integer determined so that 2n is larger than ?), and calculates the pixel value of the target pixel from the 2n-times enlarged image data through interpolation processing of pixel values of pixels of the 2n-times enlarged image corresponding to the target pixel of the ?-times enlarged image.

Abstract: A host device divides original data into first to Nth stream data for N being an integer of two or more, generates first to Nth compressed stream data by sequentially compressing the first to Nth stream data with a variable length compression, divides the first to Nth compressed stream data into fixed-length blocks, and sequentially transmits the fixed-length blocks to the display driver. The display driver includes a memory storing therein the fixed-length blocks and a decompression circuitry reading out the fixed-length blocks from the memory. The decompression circuitry includes first to Nth processing circuits. The first to Nth processing circuits each perform a predetermined process on the fixed-length blocks received to generate processed data. The host device sorts the fixed-length blocks so that the fixed-length blocks are supplied in the order in which the first to Nth processing circuits require the fixed-length blocks.

Abstract: A data transmission system for a display device, the data transmission system comprising: an encoder having at least one translation table, encoding m bits of a data into n bits of a data on the basis of the translation table; a parallel-to-serial converter; a clock recovery circuit for recovering a clock from the data encoded and serialized; a serial-to-parallel converter for decoding the n bits of the encoded data to the m bits of the data; and an output driver for outputting a gray scale voltage, wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and, wherein in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2 m pieces of bit patterns of the m bits of the data, a larger the data change index of the bit pattern.

Abstract: An image processing circuit includes: a representative-values calculation circuit and an all-combinations comparing compression circuit. The representative-values calculation circuit is configured to generate M datasets each including a plurality of representative values by performing a pre-process on image data associated with said N pixels, M being a natural number more than one and less than N. The all-combinations comparing compression circuit is configured to calculate correlations between two datasets selected from said M datasets for all possible combinations of the two datasets, to select a compression process from a plurality of compression processes in response to the calculated correlations, and to generate said compressed imaged data by compressing said M datasets by using said selected compression process. The image processing circuit may be incorporated in a display panel driver.

Abstract: A display driver for driving a display panel includes a voltage data generator circuit calculating a voltage data value from an input grayscale value and a driver circuitry driving the display panel in response to the voltage data value. The voltage data generator circuit includes a basic control point data storage circuit storing therein basic control point data specifying a basic correspondence relationship between the input grayscale value and the voltage data value, a correction data memory storing correction data for each of the pixel circuits, a control point calculation circuit and a data correction circuit.

Abstract: A host device divides original data into first to Nth stream data for N being an integer of two or more, generates first to Nth compressed stream data by sequentially compressing the first to Nth stream data with a variable length compression, divides the first to Nth compressed stream data into fixed-length blocks, and sequentially transmits the fixed-length blocks to the display driver. The display driver includes a memory storing therein the fixed-length blocks and a decompression circuitry reading out the fixed-length blocks from the memory. The decompression circuitry includes first to Nth processing circuits. The first to Nth processing circuits each perform a predetermined process on the fixed-length blocks received to generate processed data. The host device sorts the fixed-length blocks so that the fixed-length blocks are supplied in the order in which the first to Nth processing circuits require the fixed-length blocks.

Abstract: A system and method for controlling the screen brightness of a display comprising calculating a brightness data which specifies a screen brightness level of a self-luminous display panel, determining, based on the brightness data, correction control points, calculating an output value from the input grayscale value with input-output characteristics specified by the correction control points.

Abstract: A system and method for rendering subpixels comprising performing an eight-color halftoning process on the second image data to generate third image data which describe a grayscale value of each of an R subpixel, a G subpixel and a B subpixel of each pixel with one bit, generating the third image data by performing a dithering process on the second image data using a dither value selected from elements of the dither table, when the third image data associated with a pixel of interest of the display panel is generated, and driving the display panel in response to the third image data.

Abstract: A display panel driver includes an image data generator, a brightness correction circuit performing a correction calculation on image data, a drive section driving the display panel in response to corrected image data; and a display timing generator outputting a timing control signal. The correction calculation by the brightness correction circuit is adjustable. When the display panel driver is placed into a test mode, the display timing generator is configured to output an internally-generated timing control signal and the image data generator outputs internally-generated evaluation image data. The evaluation image data are generated so that the evaluation images are switched from one to another in response to the internally-generated timing control signal.

Abstract: A display panel driver includes: a correction calculation section which performs correction calculations on input image data to generate saturation-enhanced output image data and a drive circuitry driving the display panel in response to the output image data and a starting point control section. The correction calculation section generates red (R) data, green (G) data and blue (B) data of the output image data by performing the correction calculations on R data, G data and B data of the input image data, respectively. The starting point control section controls the positions of starting points of the input-output curves of the correction calculations.

Abstract: Techniques for displaying a quality-improved image with reduced power consumption are provided. In one embodiment, a display panel driver is provided that includes a dithering section configured to receive first m-bit image data and configured to generate second image data by performing dithering on the first image data with n-bit dither values each selected from elements of a dither table, and a driver circuit configured to drive the source lines of a display panel in response to the second image data. In generating the second image data corresponding to first pixels belonging to a first pixel column, the dither values are selected from elements in a first column of the dither table, while the second image data corresponding to second pixels belonging to a second pixel column adjacent to the first pixel column, the dither values are selected from elements in a second column of the dither table.

Abstract: A display apparatus includes: a display device; a display device driver which drives the display device; a compression section adapted to an operation of generating compression data by compression processing performed on image data; and a transmission section which, when receiving compressed data from the compression section, transmits the compressed data to the display device driver by using a serial data signal. The compression section performs the compression processing with a data compression ratio selected in response to a frame rate with which the display device driver drives the display device. The display device driver receives the serial data signal from the transmission section, generates decompressed data by decompressing the compressed data transmitted by the serial data signal, and drives the display device in response to the decompressed data.

Abstract: A display panel driver includes an image data generator, a brightness correction circuit performing a correction calculation on image data, a drive section driving the display panel in response to corrected image data; and a display timing generator outputting a timing control signal. The correction calculation by the brightness correction circuit is adjustable. When the display panel driver is placed into a test mode, the display timing generator is configured to output an internally-generated timing control signal and the image data generator outputs internally-generated evaluation image data. The evaluation image data are generated so that the evaluation images are switched from one to another in response to the internally-generated timing control signal.

Abstract: A display panel driver includes: a correction calculation section which performs correction calculations on input image data to generate saturation-enhanced output image data and a drive circuitry driving the display panel in response to the output image data and a starting point control section. The correction calculation section generates red (R) data, green (G) data and blue (B) data of the output image data by performing the correction calculations on R data, G data and B data of the input image data, respectively. The starting point control section controls the positions of starting points of the input-output curves of the correction calculations.

Abstract: Techniques for displaying a quality-improved image with reduced power consumption are provided. In one embodiment, a display panel driver is provided that includes a dithering section configured to receive first m-bit image data and configured to generate second image data by performing dithering on the first image data with n-bit dither values each selected from elements of a dither table, and a driver circuit configured to drive the source lines of a display panel in response to the second image data. In generating the second image data corresponding to first pixels belonging to a first pixel column, the dither values are selected from elements in a first column of the dither table, while the second image data corresponding to second pixels belonging to a second pixel column adjacent to the first pixel column, the dither values are selected from elements in a second column of the dither table.

Abstract: A display device includes a display panel; and a display panel driver driving the display panel. The display panel driver includes: a processing circuit configured to perform digital arithmetic processing on R, G and B grayscale values of input image data to calculate R, G and B grayscale values of output image data, respectively, and a control point data generation circuit configured to: generate first control point data indicating the shape of a desired gamma curve; calculate Re, G and B control point data indicating input-output curves of digital arithmetic processing performed on the R, G and B grayscale values of the input image data by correcting the first control point data in response to the input image data. The processing circuit is configured to calculate the R, G and B grayscale values of the output image data in response to the R, G and B control point data.