Patents by Inventor Hirobumi Inoue
Hirobumi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9283812Abstract: A pneumatic radial tire for heavy loads that prevents occurrence of a side cut due to a projection while decelerating spread of a cut damage to a tire inner surface. In a widthwise cross section of the tire, angle ? satisfies a relation 0<??30° that a line joining an intersection between a virtual line and a tire outer surface and a maximum tire width position forms with respect to a radial line segment, the virtual line passing through a maximum carcass width position that is parallel to a tire axis line. An angle ? satisfies a relation 0??<30° that a line joining the maximum tire width position and a turnoff point forms with respect to the radial line segment, and a reinforcing rubber is disposed between a body portion and a turn-up portion of the carcass.Type: GrantFiled: November 25, 2010Date of Patent: March 15, 2016Assignee: BRIDGESTONE CORPORATIONInventor: Hirobumi Inoue
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Publication number: 20120247638Abstract: A pneumatic radial tire for heavy loads that prevents occurrence of a side cut due to a projection while decelerating spread of a cut damage to a tire inner surface. In a widthwise cross section of the tire, angle ? satisfies a relation 0<??30° that a line joining an intersection between a virtual line and a tire outer surface and a maximum tire width position forms with respect to a radial line segment, the virtual line passing through a maximum carcass width position that is parallel to a tire axis line. An angle ? satisfies a relation 0??<30° that a line joining the maximum tire width position and a turnoff point forms with respect to the radial line segment, and a reinforcing rubber is disposed between a body portion and a turn-up portion of the carcass.Type: ApplicationFiled: November 25, 2010Publication date: October 4, 2012Applicant: BRIDGESTONE CORPORATIONInventor: Hirobumi Inoue
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Publication number: 20100032198Abstract: An inclined peripheral portion 103 having a tapered shape in a cross-sectional view, in which the thickness thereof is reduced toward the edge of an interconnection substrate 102, is provided at the edge of the interconnection substrate 102. In addition, inner layers 112 are provided such that the distance therebetween is reduced toward the edge of the interconnection substrate in the inclined peripheral portion 103. A first interconnection conductor 104 and a second interconnection conductor 105 are provided on both inclined planes of the inclined peripheral portion 103 so as to be electrically connected to each other at the leading end of the inclined peripheral portion 103.Type: ApplicationFiled: February 20, 2008Publication date: February 11, 2010Inventor: Hirobumi Inoue
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Patent number: 7594644Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: GrantFiled: November 7, 2005Date of Patent: September 29, 2009Assignee: NEC CorporationInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
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Patent number: 7434190Abstract: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.Type: GrantFiled: June 23, 2006Date of Patent: October 7, 2008Assignee: NEC CorporationInventors: Hirobumi Inoue, Daisuke Ohshima, Jun Sakai, Mitsuru Furuya
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Patent number: 7321166Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.Type: GrantFiled: November 16, 2005Date of Patent: January 22, 2008Assignees: NEC Corporation, NEC Electronics CorporationInventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga
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Publication number: 20070033564Abstract: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.Type: ApplicationFiled: June 23, 2006Publication date: February 8, 2007Inventors: Hirobumi Inoue, Daisuke Ohshima, Jun Sakai, Mitsuru Furuya
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Publication number: 20060103004Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.Type: ApplicationFiled: November 16, 2005Publication date: May 18, 2006Inventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga
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Publication number: 20060055053Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: ApplicationFiled: November 7, 2005Publication date: March 16, 2006Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
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Patent number: 6998704Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: GrantFiled: August 21, 2003Date of Patent: February 14, 2006Assignee: NEC CorporationInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
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Publication number: 20040115920Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.Type: ApplicationFiled: August 21, 2003Publication date: June 17, 2004Applicant: NEC CORPORATIONInventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
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Patent number: 6486688Abstract: A semiconductor device testing apparatus that has a laminate structure composed of a contact sheet having a first opening, an elastic sheet having a second opening and a base plate having a third opening. A supply voltage is applied to an external terminal located on a peripheral portion of the contact sheet. A probe of a probe portion is contacted to a signal electrode of a semiconductor device through the third, second and first openings.Type: GrantFiled: September 20, 2001Date of Patent: November 26, 2002Assignee: NEC CorporationInventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
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Patent number: 6433410Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.Type: GrantFiled: March 30, 2001Date of Patent: August 13, 2002Assignee: NEC CorporationInventors: Michinobu Tanioka, Takahiro Kimura, Hirobumi Inoue, Hiroo Ito, Yoshihito Fukasawa
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Patent number: 6400168Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.Type: GrantFiled: June 22, 2001Date of Patent: June 4, 2002Assignees: NEC Corporation, Anritsu CorporationInventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
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Publication number: 20020036514Abstract: There is provided a semiconductor device testing apparatus that can perform a measurement of an electrical characteristic of a semiconductor device that has many electrodes and operates at high frequency. The semiconductor device testing apparatus comprises: a contact sheet (105) having supply voltage electrodes (107c, 107b) of bump structure on a thin insulator sheet (105a), which contact with a source electrode (100c) and a ground electrode (100b) of a semiconductor device (100), and a first opening (113) located at a position facing a signal (100a) of the semiconductor device (100).Type: ApplicationFiled: September 20, 2001Publication date: March 28, 2002Applicant: NEC CORPORATIONInventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
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Publication number: 20010038294Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.Type: ApplicationFiled: June 22, 2001Publication date: November 8, 2001Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
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Patent number: 6310483Abstract: A high-frequency probe according to the present invention comprises a probe chip that has an end part that is pressed to an electrode and is covered by a electrically conductive outer enclosure, and slides in a vertical direction by an inner surface of this electrically conductive outer enclosure inside this electrically conductive outer enclosure. A signal conductive pattern is fixed inside this probe chip and is connected with a inner conductor having elasticity. The inner conductor can be bent in the vertical direction at a central part of a hole having an opening, which is sufficiently long in the vertical direction, in the center space of a ground conductor, which is fixed to an end part of the main block, when the inner conductor is pressed due to contact of the end part. In addition, the high-frequency probe has a thin shape of a maximum thickness in a transverse direction which is perpendicular to the vertical direction that is a direction of the probe being pressed to a device electrode.Type: GrantFiled: October 30, 1998Date of Patent: October 30, 2001Assignees: NEC Corporation, Anritsu CorporationInventors: Toru Taura, Hirobumi Inoue, Masao Tanehashi, Kouji Matsunaga, Yuuichi Yamagishi, Satoshi Hayakawa, Hironori Tsugane
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Publication number: 20010033010Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.Type: ApplicationFiled: March 30, 2001Publication date: October 25, 2001Inventors: Michinobu Tanioka, Takahiro Kimura, Hirobumi Inoue, Hiroo Ito, Yoshihito Fukasawa
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Patent number: 6281691Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block . A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.Type: GrantFiled: June 9, 1999Date of Patent: August 28, 2001Assignees: NEC Corporation, Amritsu CorporationInventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
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Patent number: 6242930Abstract: In a high-frequency probe having a detachable end according to the present invention, parts relating to replacement of an end unit are three parts, that is, an end unit, a probe body, and a pressure block. The end unit comprises a coaxial cable, two slender plate-like ground plates. The coaxial cable is linear in the direction of the end of the high-frequency probe. The ground plates sandwich the coaxial cable. The probe body has an end unit support surface, a circuit board, an end unit arrangement surface and an end part guide. The end unit support surface forms a perpendicular surface used for fixing the end unit to a predetermined position in the end side of the central block in a central part of a surface of the body block. The circuit board connects the end unit to a coaxial connector. The end unit arrangement surface forms a plane in an end side of the body block. And further the guide groove positions and fixes the ground plate in the end part.Type: GrantFiled: November 20, 1998Date of Patent: June 5, 2001Assignees: NEC Corporation, Antritsu CorporationInventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa, Hironori Tsugane