Patents by Inventor Hirobumi Inoue

Hirobumi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220206426
    Abstract: An electro-conductive member for an electrophotographic image forming apparatus for which a change in resistance value is small even when a large current is applied at a high voltage for a long period of time is provided. The electro-conductive member includes a support having an electro-conductive outer surface and an electro-conductive layer on the outer surface of the support, in which the electro-conductive layer has a matrix including a cross-linked product of a first rubber and domains dispersed in the matrix, the domains include a cross-linked product of a second rubber different from the first rubber and an electrically conductive agent, and the cross-linked product of the second rubber has, in a molecule, a structural unit represented by Structural Formula (I). [—(CH2)n—O—]??Structural Formula (I) In Structural Formula (I), n is an integer of 1 to 3.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Inventors: Hirobumi Takahashi, Shota Segawa, Syoji Inoue
  • Patent number: 9283812
    Abstract: A pneumatic radial tire for heavy loads that prevents occurrence of a side cut due to a projection while decelerating spread of a cut damage to a tire inner surface. In a widthwise cross section of the tire, angle ? satisfies a relation 0<??30° that a line joining an intersection between a virtual line and a tire outer surface and a maximum tire width position forms with respect to a radial line segment, the virtual line passing through a maximum carcass width position that is parallel to a tire axis line. An angle ? satisfies a relation 0??<30° that a line joining the maximum tire width position and a turnoff point forms with respect to the radial line segment, and a reinforcing rubber is disposed between a body portion and a turn-up portion of the carcass.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: March 15, 2016
    Assignee: BRIDGESTONE CORPORATION
    Inventor: Hirobumi Inoue
  • Publication number: 20120247638
    Abstract: A pneumatic radial tire for heavy loads that prevents occurrence of a side cut due to a projection while decelerating spread of a cut damage to a tire inner surface. In a widthwise cross section of the tire, angle ? satisfies a relation 0<??30° that a line joining an intersection between a virtual line and a tire outer surface and a maximum tire width position forms with respect to a radial line segment, the virtual line passing through a maximum carcass width position that is parallel to a tire axis line. An angle ? satisfies a relation 0??<30° that a line joining the maximum tire width position and a turnoff point forms with respect to the radial line segment, and a reinforcing rubber is disposed between a body portion and a turn-up portion of the carcass.
    Type: Application
    Filed: November 25, 2010
    Publication date: October 4, 2012
    Applicant: BRIDGESTONE CORPORATION
    Inventor: Hirobumi Inoue
  • Publication number: 20100032198
    Abstract: An inclined peripheral portion 103 having a tapered shape in a cross-sectional view, in which the thickness thereof is reduced toward the edge of an interconnection substrate 102, is provided at the edge of the interconnection substrate 102. In addition, inner layers 112 are provided such that the distance therebetween is reduced toward the edge of the interconnection substrate in the inclined peripheral portion 103. A first interconnection conductor 104 and a second interconnection conductor 105 are provided on both inclined planes of the inclined peripheral portion 103 so as to be electrically connected to each other at the leading end of the inclined peripheral portion 103.
    Type: Application
    Filed: February 20, 2008
    Publication date: February 11, 2010
    Inventor: Hirobumi Inoue
  • Patent number: 7594644
    Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: September 29, 2009
    Assignee: NEC Corporation
    Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
  • Patent number: 7434190
    Abstract: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: October 7, 2008
    Assignee: NEC Corporation
    Inventors: Hirobumi Inoue, Daisuke Ohshima, Jun Sakai, Mitsuru Furuya
  • Patent number: 7321166
    Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: January 22, 2008
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga
  • Publication number: 20070033564
    Abstract: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.
    Type: Application
    Filed: June 23, 2006
    Publication date: February 8, 2007
    Inventors: Hirobumi Inoue, Daisuke Ohshima, Jun Sakai, Mitsuru Furuya
  • Publication number: 20060103004
    Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 18, 2006
    Inventors: Jun Sakai, Hirobumi Inoue, Kazuhiro Motonaga
  • Publication number: 20060055053
    Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.
    Type: Application
    Filed: November 7, 2005
    Publication date: March 16, 2006
    Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
  • Patent number: 6998704
    Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: February 14, 2006
    Assignee: NEC Corporation
    Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
  • Publication number: 20040115920
    Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.
    Type: Application
    Filed: August 21, 2003
    Publication date: June 17, 2004
    Applicant: NEC CORPORATION
    Inventors: Takao Yamazaki, Hirobumi Inoue, Ichiro Hazeyama, Sakae Kitajo, Masahiro Kubo, Yoshimichi Sogawa, Hidehiko Kuroda
  • Patent number: 6486688
    Abstract: A semiconductor device testing apparatus that has a laminate structure composed of a contact sheet having a first opening, an elastic sheet having a second opening and a base plate having a third opening. A supply voltage is applied to an external terminal located on a peripheral portion of the contact sheet. A probe of a probe portion is contacted to a signal electrode of a semiconductor device through the third, second and first openings.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: November 26, 2002
    Assignee: NEC Corporation
    Inventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
  • Patent number: 6433410
    Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 13, 2002
    Assignee: NEC Corporation
    Inventors: Michinobu Tanioka, Takahiro Kimura, Hirobumi Inoue, Hiroo Ito, Yoshihito Fukasawa
  • Patent number: 6400168
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: June 4, 2002
    Assignees: NEC Corporation, Anritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
  • Publication number: 20020036514
    Abstract: There is provided a semiconductor device testing apparatus that can perform a measurement of an electrical characteristic of a semiconductor device that has many electrodes and operates at high frequency. The semiconductor device testing apparatus comprises: a contact sheet (105) having supply voltage electrodes (107c, 107b) of bump structure on a thin insulator sheet (105a), which contact with a source electrode (100c) and a ground electrode (100b) of a semiconductor device (100), and a first opening (113) located at a position facing a signal (100a) of the semiconductor device (100).
    Type: Application
    Filed: September 20, 2001
    Publication date: March 28, 2002
    Applicant: NEC CORPORATION
    Inventors: Toru Taura, Hirobumi Inoue, Michinobu Tanioka, Takahiro Kimura, Kouji Matsunaga
  • Publication number: 20010038294
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block. A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Application
    Filed: June 22, 2001
    Publication date: November 8, 2001
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa
  • Patent number: 6310483
    Abstract: A high-frequency probe according to the present invention comprises a probe chip that has an end part that is pressed to an electrode and is covered by a electrically conductive outer enclosure, and slides in a vertical direction by an inner surface of this electrically conductive outer enclosure inside this electrically conductive outer enclosure. A signal conductive pattern is fixed inside this probe chip and is connected with a inner conductor having elasticity. The inner conductor can be bent in the vertical direction at a central part of a hole having an opening, which is sufficiently long in the vertical direction, in the center space of a ground conductor, which is fixed to an end part of the main block, when the inner conductor is pressed due to contact of the end part. In addition, the high-frequency probe has a thin shape of a maximum thickness in a transverse direction which is perpendicular to the vertical direction that is a direction of the probe being pressed to a device electrode.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: October 30, 2001
    Assignees: NEC Corporation, Anritsu Corporation
    Inventors: Toru Taura, Hirobumi Inoue, Masao Tanehashi, Kouji Matsunaga, Yuuichi Yamagishi, Satoshi Hayakawa, Hironori Tsugane
  • Publication number: 20010033010
    Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 25, 2001
    Inventors: Michinobu Tanioka, Takahiro Kimura, Hirobumi Inoue, Hiroo Ito, Yoshihito Fukasawa
  • Patent number: 6281691
    Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block . A plurality of the signal lines may be arranged in parallel on the same plane of the substrate.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: August 28, 2001
    Assignees: NEC Corporation, Amritsu Corporation
    Inventors: Kouji Matsunaga, Hirobumi Inoue, Masao Tanehashi, Toru Taura, Masahiko Nikaidou, Yuuichi Yamagishi, Satoshi Hayakawa