Patents by Inventor Hirobumi Matsuki
Hirobumi Matsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7400007Abstract: A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.Type: GrantFiled: December 19, 2005Date of Patent: July 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Yusuke Kawaguchi, Yoshihiro Yamaguchi, Hirobumi Matsuki, Kiyotaka Arai
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Publication number: 20060157778Abstract: A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.Type: ApplicationFiled: December 19, 2005Publication date: July 20, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Syotaro Ono, Yusuke Kawaguchi, Yoshihiro Yamaguchi, Hirobumi Matsuki, Kiyotaka Arai
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Patent number: 6992351Abstract: A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.Type: GrantFiled: June 28, 2004Date of Patent: January 31, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hirobumi Matsuki, Tsuyoshi Oota, Yuji Hiyama
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Publication number: 20050247974Abstract: A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.Type: ApplicationFiled: May 31, 2005Publication date: November 10, 2005Inventors: Hirobumi Matsuki, Akio Takano, Takahiro Kawano
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Publication number: 20050224887Abstract: A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.Type: ApplicationFiled: June 28, 2004Publication date: October 13, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hirobumi Matsuki, Tsuyoshi Oota, Yuji Hiyama
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Patent number: 6940128Abstract: A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.Type: GrantFiled: June 28, 2004Date of Patent: September 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hirobumi Matsuki, Tsuyoshi Oota, Yuji Hiyama
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Patent number: 6930355Abstract: A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.Type: GrantFiled: May 16, 2003Date of Patent: August 16, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hirobumi Matsuki, Akio Takano, Takahiro Kawano
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Patent number: 6919249Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.Type: GrantFiled: February 17, 2004Date of Patent: July 19, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takahiro Kawano, Tatsuo Yoneda, Hirobumi Matsuki
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Publication number: 20040159885Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.Type: ApplicationFiled: February 17, 2004Publication date: August 19, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takahiro Kawano, Tatsuo Yoneda, Hirobumi Matsuki
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Patent number: 6750511Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.Type: GrantFiled: September 19, 2002Date of Patent: June 15, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Takahiro Kawano, Tatsuo Yoneda, Hirobumi Matsuki
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Publication number: 20040026753Abstract: A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.Type: ApplicationFiled: May 16, 2003Publication date: February 12, 2004Inventors: Hirobumi Matsuki, Akio Takano, Takahiro Kawano
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Publication number: 20030075759Abstract: A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.Type: ApplicationFiled: September 19, 2002Publication date: April 24, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takahiro Kawano, Tatsuo Yoneda, Hirobumi Matsuki