Patents by Inventor Hiroe Kami

Hiroe Kami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read
    Patent number: 10643715
    Abstract: A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Konno, Yoshikazu Harada, Kosuke Yanagidaira, Jun Nakai, Hiroe Kami, Yuko Utsunomiya
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM CONFIGURED TO PERFORM TRACKING READ ON FIRST MEMORY CELLS FOLLOWED BY SHIFT READ ON SECOND MEMORY CELLS USING READ VOLTAGE CORRECTION VALUE DETERMINED DURING THE TRACKING READ
    Publication number: 20190115085
    Abstract: A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
    Type: Application
    Filed: November 19, 2018
    Publication date: April 18, 2019
    Inventors: Hayato KONNO, Yoshikazu HARADA, Kosuke YANAGIDAIRA, Jun NAKAI, Hiroe KAMI, Yuko UTSUNOMIYA
  • Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read
    Patent number: 10163517
    Abstract: A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Konno, Yoshikazu Harada, Kosuke Yanagidaira, Jun Nakai, Hiroe Kami, Yuko Utsunomiya
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20180090212
    Abstract: A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 29, 2018
    Inventors: Hayato KONNO, Yoshikazu HARADA, Kosuke YANAGIDAIRA, Jun NAKAI, Hiroe KAMI, Yuko UTSUNOMIYA
  • Semiconductor memory device and memory system
    Patent number: 9859011
    Abstract: A semiconductor memory device includes first and second memory cells, first and second word lines that are respectively connected to gates of the first and second memory cells, and a control circuit that executes first and second read operations in response to first and second command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line, and a second read sequence, in which the control circuit reads data by applying a first read voltage that is set based on the result of the first read sequence, to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on the result of the first read sequence of the first read operation, to the second word line.
    Type: Grant
    Filed: February 26, 2017
    Date of Patent: January 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Konno, Yoshikazu Harada, Kosuke Yanagidaira, Jiyun Nakai, Hiroe Kami, Yuko Utsunomiya