Patents by Inventor Hiroei ARAKI

Hiroei ARAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses for refreshing memory of a semiconductor device
    Patent number: 11056167
    Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yoshifumi Mochida, Hiroei Araki
  • APPARATUSES FOR REFRESHING MEMORY OF A SEMICONDUCTOR DEVICE
    Publication number: 20200058346
    Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of defective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yoshifumi Mochida, Hiroei Araki
  • Apparatuses for refreshing memory of a semiconductor device
    Patent number: 10490250
    Abstract: Disclosed herein is an apparatus that includes a memory cell array, a row hammer refresh circuit configured to generate a row hammer refresh address based on an access history of the memory cell array, a redundancy circuit configured to store a plurality of detective addresses of the memory cell array, and a row pre-decoder configured to skip a refresh operation on the row hammer refresh address when the row hammer refresh address matches any one of the plurality of defective addresses.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yoshifumi Mochida, Hiroei Araki
  • Impedance adjustment circuit with correction circuit for semiconductor device
    Patent number: 8878564
    Abstract: A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hiroei Araki
  • SEMICONDUCTOR DEVICE
    Publication number: 20130015879
    Abstract: A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiroei ARAKI