Patents by Inventor Hirofumi Abe

Hirofumi Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5855334
    Abstract: A rectangular parallelepipedic case includes four or more walls formed by bending a single plate. To produce the case, a double plate is used. The double plate is formed from plastic by extrusion, and first and second plate elements confronted with each other. Partition portions interconnect the first and second plate elements, and extend in the direction of the extrusion, to define plural hollow chambers between the first and second plate elements. The double plate is bent along bend lines substantially at a right angle. At least one of the bend lines is at least partially curved.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: January 5, 1999
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hirofumi Abe, Akihisa Inoue, Shinichi Takahashi
  • Patent number: 5846211
    Abstract: An occlusal force-meter 1 includes an occlusal force detecting portion 2 for detecting an occlusal force and a main body 3 for processing the detected signal obtained by the occlusal force detecting portion 2 to display the occlusal force measured value on a display 4. The occlusal force detecting portion 2 includes a transmitting portion (second pressure transmitting portion) 5 having diaphragm portions 7, 8 at an upper surface and/or a lower surface of one end portion 5f thereof. A pressure medium liquid L is filed therein, for transmitting the occlusal force added to the diaphragm portions 7, 8 to a pressure detector 9 disposed on the other end portion 5r thereof.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: December 8, 1998
    Assignee: Nagano Keiki Seisakusho, Ltd.
    Inventors: Masao Sakaguchi, Junichi Yoshiike, Hiroaki Tsuruta, Hirofumi Abe
  • Patent number: 5806786
    Abstract: A container, for example a photographic paper magazine, includes a core about which photographic paper is wound in a form of a roll. A container body contains the roll with the core in a rotatable manner. An outlet slit is formed in the container body and adapted to drawing out the photographic paper. First and second end walls are disposed on the container body, and confronted with respective end faces of the roll. First and second core supports are supported respectively on the first and second end walls, rotatable coaxially, and fitted on respective axial ends of the core. The core supports support the core between the end walls in a rotatable manner. A lock pin is fixedly secured to the first end wall. A hook is disposed on the first core support, is engageable with the lock pin in a resilient manner, and inhibits relative rotation between the hook and the lock pin, to retain the first core support on the first end wall.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: September 15, 1998
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hirofumi Abe, Hiroyuki Iwasa
  • Patent number: 5716864
    Abstract: A first insulating film for the formation of a gate insulating film is formed on a semiconductor substrate having a memory cell forming region and a peripheral transistor forming region. A first conductive film for the formation of a floating gate is formed on the first insulating film, and a second insulating film is formed on the first conductive film. A second conductive film is formed on the second insulating film for protecting the second insulating film, and a protective film performing the functions of an oxidation-resistant film, a washing-resistant film and an etching resistant film is formed on the second conductive film. Then, the peripheral transistor region is subjected to a predetermined process. A third conductive film, which will become a control gate of the memory cell and a gate of the peripheral transistor, is formed on the second conductive film and the peripheral transistor forming region subjected to the predetermined process.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: February 10, 1998
    Assignee: NKK Corporation
    Inventor: Hirofumi Abe
  • Patent number: 5625218
    Abstract: A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: April 29, 1997
    Assignees: Nippondenso Co., Ltd., Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Hideya Yamadera, Takeshi Ohwaki, Yasunori Taga, Makio Iida, Makoto Ohkawa, Hirofumi Abe, Yoshihiko Isobe
  • Patent number: 5623442
    Abstract: An object of the present invention is to provide a DRAM of a special form, a non-volatile memory cell incorporating the DRAM, and a semiconductor device which incorporates a DRAM structure and a non-volatile memory cell and where data can be written and erased with high accuracy. The semiconductor memory device has a sub bit line BLs1 to which the main bit line BL1 is connected via a selector transistor Tr1, and non-volatile memory cells M1-Nn, i.e., memory transistors whose drain electrodes are connected to the sub bit line Bls1. An a-c pulse generator applies an a-c voltage to the control gates of the non-volatile memory cells M1-Nn. The DRAM cell is formed of a capacitor element formed of parasitic capacitance of the sub bit line BLs1 and the drain electrodes of the non-volatile memory cells connected to the bit line BLs1.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: April 22, 1997
    Assignee: NKK Corporation
    Inventors: Hiroshi Gotou, Mamoru Kondo, Hirofumi Abe
  • Patent number: 5444650
    Abstract: A programmable semiconductor memory cell is provided; which secures a sufficient output signal voltage margin and which also has reduced current dissipation and improved durability. To program the programmable semiconductor memory cell of this invention, a high write potential is applied to the high-level lead of a fuse and a selector transistor is turned on to blow the fuse. When reading the memory cell, high read potential is applied to the high-level lead of the fuse. Because an emitter and base of an output transistor are connected to both leads of the fuse, the output transistor is turned on when the fuse is blown and is turned off when the fuse is not blown. The output transistor outputs an amplified signal voltage to an output line.
    Type: Grant
    Filed: January 25, 1994
    Date of Patent: August 22, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hirofumi Abe, Tadashi Shibata