Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus capable of achieving a high resolution and a high dynamic range by arranging a large-sized pixel transistor in a case where only one pixel transistor other than a transfer transistor is arrangeable within one pixel. The solid-state imaging device includes a pixel array unit that includes pixels each having a photoelectric conversion element, a floating diffusion region, a transfer transistor, and one pixel transistor other than a transfer transistor, the pixels being two-dimensionally arranged in a matrix shape. The one pixel transistor is any one of a reset transistor, a switching transistor, an amplification transistor, or a selection transistor. The present disclosure is applicable to a solid-state imaging device having small-sized pixels, for example.

Abstract: A transfer apparatus comprising a first switch configured to generate a first timing pulse based on a reference clock, transmit first information related to the first timing pulse, a second switch configured to, generate a second timing pulse based on the reference clock, transmit second information related to the second timing pulse, a line interface configured to receive signal data and store the signal data in a memory, transfer the signal data based on the first timing pulse when the first information is received, and transfer the signal data based on the information when the first information is not received and the second information is received, detect a phase shift between the first timing pulse and the second timing pulse, transmit the phase shift to the second switch, wherein the second switch is configured to correct, based on the phase shift, a timing that the second timing pulse is generated.

Abstract: A method of fault notification in a communication apparatus, including terminating transmission of a signal over a transmission link; determining whether or not a specified fault notification signal is detected in a reception link and storing a determination result from the determining; and upon detection of a fault in the reception link after starting an operation, outputting a specified fault notification signal to the transmission link when the stored determination result is affirmative.

Abstract: In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard controller controls discard operation of the data read out of the temporary memory.

Abstract: A method of fault notification in a communication apparatus, including terminating transmission of a signal over a transmission link; determining whether or not a specified fault notification signal is detected in a reception link and storing a determination result from the determining; and upon detection of a fault in the reception link after starting an operation, outputting a specified fault notification signal to the transmission link when the stored determination result is affirmative.

Abstract: In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard controller controls discard operation of the data read out of the temporary memory.

Abstract: A dynamic memory management method and apparatus wherein an area of a memory is partitioned into a plurality of areas to form memory banks. The different priority classes share the memory banks. A policer (write controller) dynamically assigns input frame data of a plurality of classes having different degrees of priority to memory banks in accordance with the degrees of priority and stores the data there for each priority class. A scheduler (read controller) sequentially reads out the data from the frame data stored in the memory bank assigned to the class having the highest degree of priority and transmits the same. For storage of frame data of a priority of class input in a burst like manner, a plurality of memory banks are assigned to that priority class so as to raise the burst tolerance. By controlling writing and reading of data in units of memory banks, the control can be simplified. Due to this, the efficiency of usage of memory is improved and the write/read control is simplified.

Abstract: In a monitoring device and system, a monitoring data inserter inserts monitoring data of a predetermined pattern into an idle period of input data to be transmitted to a transmission line. A monitoring data checker having received the monitoring data through the transmission line, when determining that the monitoring data does not maintain the predetermined pattern, provides selective switchover instructions to a selector to be controlled. Then, the monitoring data checker sequentially performs a selective switchover to processors, thereby detecting a failure point in the processors. Also, when the failure point in the processors can not be detected, the monitoring data checker provides channel switchover instructions to a switching portion and performs a channel switchover of the transmission line, thereby detecting which channel of the transmission line has caused a failure.