Abstract: A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Abstract: A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.

Abstract: A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when “delay time td+allowance time ta” has elapsed from a start signal Sp. The delay time td is shorter than “the minimum time width of H level of PWM signal SPWM1?allowance time ta”. The delay time td is also time from the variation of level of the PWM signal SPWM1 to actual variation in the passage of current through a power section.

Abstract: In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.

Abstract: A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.

Abstract: A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Abstract: In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.

Abstract: A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when “delay time td+allowance time ta” has elapsed from a start signal Sp. The delay time td is shorter than “the minimum time width of H level of PWM signal SPWM1−allowance time ta”. The delay time td is also time from the variation of level of the PWM signal SPWM1 to actual variation in the passage of current through a power section.

Abstract: A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter. and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Abstract: A data conversion device for converting analog data to digital data, or digital data to analog data, is composed of a data converter and a mediator. Plural data groups are fed to the data converter that coverts the data, group by group, upon receipt of a request for converting a particular data group. If plural requests are simultaneously made, the mediator makes mediation among the plural requests to select a data group to be first converted and to set a priority order. A function uniquely corresponding to a combination of the plural requests is generated in the mediator, and the mediation is performed based on the generated function with reference to a preinstalled table showing a relation between the function and the request to be selected.

Abstract: A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal.

Abstract: To provide a time measuring apparatus which is compact and capable of highly accurate measurements, on a semiconductor chip, flip-flops constituting a delayed-signal holding circuit of a first channel and flip-flops constituting a delayed-signal holding circuit of a second channel are disposed alternatingly and in a single row in a circuit region of the delayed-signal holding circuits to latch delayed signals from a pulse-circulating circuit, and flip-flops for latching the same delay signals are mutually adjacent. Due to this, distances between the pulse-circulating circuit and the respective delayed-signal holding circuits become equal, and delay signals having no deviation in delay due to difference in wiring length are supplied to the respective channels, and so uniform measurement can be performed between the respective channels.