Patents by Inventor HIROFUMI KIDA

HIROFUMI KIDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20250261392
    Abstract: A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.
    Type: Application
    Filed: April 29, 2025
    Publication date: August 14, 2025
    Inventors: Hirofumi KIDA, Hidemoto TOMITA, Tomohiko MORI, Hideya YAMADERA
  • Semiconductor device and method for manufacturing the same
    Patent number: 12324177
    Abstract: A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: June 3, 2025
    Assignee: DENSO CORPORATION
    Inventors: Hirofumi Kida, Hidemoto Tomita, Tomohiko Mori, Hideya Yamadera
  • Semiconductor device and manufacturing method of semiconductor device
    Patent number: 11784223
    Abstract: A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: October 10, 2023
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventor: Hirofumi Kida
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220238703
    Abstract: A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Hirofumi KIDA, Hidemoto TOMITA, Tomohiko MORI, Hideya YAMADERA
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20220190113
    Abstract: A compound semiconductor layer in a semiconductor device includes a drift region of a first conductivity type, a JFET region of the first conductivity type disposed above the drift region, a body region of a second conductivity type disposed above the drift region and adjacent to the JFET region, and a JFET embedded region of the second conductivity type or i-type disposed in the JFET region. The JFET region has a bottom surface portion adjacent to the drift region, a side surface portion adjacent to the body region, and an inside portion adjacent to the JFET embedded region, and further has a high concentration portion at the bottom surface portion and the side surface portion. The high concentration portion has an impurity concentration higher than an impurity concentration of the inside portion.
    Type: Application
    Filed: November 10, 2021
    Publication date: June 16, 2022
    Inventor: HIROFUMI KIDA