Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.

Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: When a BGA package device is mounted to another substrate and tested for packaging strength, solder balls (8) frequently come detached in places where the edges of a semiconductor chip (1) align with the centers of the solder balls (8) on a BGA substrate (9) in the perpendicular direction of the substrate. In a semiconductor device of the present invention, the center of a semiconductor chip and the center of a BGA substrate to which the chip is mounted do not coincide with each other, and edges of the semiconductor chip do not align with the ball center positions on the BGA substrate in a direction perpendicular to the chip.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: When a BGA package device is mounted to another substrate and tested for packaging strength, solder balls (8) frequently come detached in places where the edges of a semiconductor chip (1) align with the centers of the solder balls (8) on a BGA substrate (9) in the perpendicular direction of the substrate. In a semiconductor device of the present invention, the center of a semiconductor chip and the center of a BGA substrate to which the chip is mounted do not coincide with each other, and edges of the semiconductor chip do not align with the ball center positions on the BGA substrate in a direction perpendicular to the chip.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.

Abstract: First and second transistors of a first conductive type of which sources are connected to two bit lines constituting a pair, respectively. The first and second transistors are disposed in a channel width direction of the transistors and in the longitudinal direction of the four-transistor memory cell on a semiconductor substrate. A third transistor of a second conductive type is provided. A drain of the third transistor is connected to a drain of the first transistor, a gate of the third transistor is connected to a drain of the second transistor and a source of the third transistor is grounded. A fourth transistor of the second conductive type is provided. A drain of the fourth transistor is connected to the drain of the second transistor, a gate of the fourth transistor is connected to the drain of the first transistor and of a source of the fourth transistor is grounded.