Abstract: A memory card control device includes an insertion unit to which a memory card is inserted, a memory card controller to control writing and reading of data to/from the memory card inserted in the insertion unit, an interface controller to send and receive the data written or read to/from the memory card to/from a host computer, a clock supplier to supply a clock signal to the memory card controller and the interface controller, a memory card detector to detect presence or absence of the memory card inserted in the insertion unit, and a low power consumption mode switching unit to switch the memory card controller and the interface controller to a low power consumption mode in response to the absence of the memory card detected by the memory card detector.

Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.

Abstract: A memory card control device includes an insertion unit to which a memory card is inserted, a memory card controller to control writing and reading of data to/from the memory card inserted in the insertion unit, an interface controller to send and receive the data written or read to/from the memory card to/from a host computer, a clock supplier to supply a clock signal to the memory card controller and the interface controller, a memory card detector to detect presence or absence of the memory card inserted in the insertion unit, and a low power consumption mode switching unit to switch the memory card controller and the interface controller to a low power consumption mode in response to the absence of the memory card detected by the memory card detector.

Abstract: A method for reading and writing a memory having n rows and A columns includes a first step of writing data in 0th to (n?2)th rows by a first technique; a second step of writing data in (n?1)th row per column and reading data in the 0th section by a second technique; a third step of writing data in 0th to (n?2)th sections by a third technique and reading data in 1st to (n?1)th sections by the second technique, a fourth step of writing data in the (n?1)th section by the third technique and reading data in 0th row by a fourth technique; a fifth step of writing data in 0th to (n?2)th rows by the first technique and reading data in 1st to (n?1)th rows by the fourth technique; and a sixth step of returning to the second step.

Abstract: Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.

Abstract: Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.