Abstract: Provided is a semiconductor manufacturing apparatus that is capable of, while holding one surface of the wafer, grinding the holding surface of a wafer. A semiconductor manufacturing apparatus includes a first main surface holding unit that comes into contact with a center portion of a first main surface of a wafer in plan view and holds the wafer, and a first grinding unit that rotates about a rotation axis that overlaps a center of the wafer in plan view and extends in a direction perpendicular to the first main surface, and that grinds an outer periphery that is a region surrounding the center portion of the first main surface in contact with the outer periphery of the first main surface.

Abstract: A semiconductor inspection apparatus includes a defect detection unit and a control unit. The defect detection unit inspects a first main surface of a semiconductor wafer including an SiC crystal having the first main surface and a second main surface and inclined at an off angle in a predetermined direction to detect a first defect which is a crystal defect included in the first main surface, and inspects the second main surface to detect a second defect which is a crystal defect included in the second main surface. The control unit controls the defect detection unit to inspect an inspection region that is a partial region of the second main surface of the semiconductor wafer when the defect detection unit detects the second defect. The inspection region is determined based on the detected position of the first defect, and the thickness and the off angle of the semiconductor wafer.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.

Abstract: A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and ?, respectively.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.

Abstract: A predetermined relational expression holds where a first distance along the in-plane direction from a channel of the first semiconductor layer to a third semiconductor layer that is the other of the collector layer and the cathode layer is designated as W, a second distance from the channel of the first semiconductor layer to the second semiconductor layer is designated as S, and a diffusion coefficient and a lifetime of a part of the semiconductor substrate between the channel of the first semiconductor layer and the third semiconductor layer are designated as D and ?, respectively.

Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.

Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.